SBAS448B October   2008  – August 2015 PCM1690

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Digital Input/Output
    6. 6.6  Electrical Characteristics: DAC
    7. 6.7  Electrical Characteristics: Power-Supply Requirements
    8. 6.8  System Clock Timing Requirements
    9. 6.9  Audio Interface Timing Requirements for Left-Justified, Right-Justified, and I2S Data Formats
    10. 6.10 Audio Interface Timing Requirements for DSP and TDM Data Formats
    11. 6.11 Three-Wire Serial Control Interface Timing Requirements
    12. 6.12 SCL and SDA Control Interface Timing Requirements
    13. 6.13 Typical Characteristics
      1. 6.13.1 Digital Filter
      2. 6.13.2 Digital De-Emphasis Filter
      3. 6.13.3 Dynamic Performance
      4. 6.13.4 Output Spectrum
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Outputs
      2. 7.3.2  Voltage Reference VCOM
      3. 7.3.3  System Clock Input
      4. 7.3.4  Sampling Mode
      5. 7.3.5  Reset Operation
      6. 7.3.6  Zero Flag
      7. 7.3.7  AMUTE Control
      8. 7.3.8  Three-Wire (SPI) Serial Control
      9. 7.3.9  Control Data Word Format
      10. 7.3.10 Register Write Operation
      11. 7.3.11 Two-Wire (I2C) Serial Control
      12. 7.3.12 Packet Protocol
      13. 7.3.13 Write Operation
      14. 7.3.14 Read Operation
      15. 7.3.15 Timing Requirements: SCL and SDA
    4. 7.4 Device Functional Modes
      1. 7.4.1 Audio Serial Port Operation
      2. 7.4.2 Audio Data Interface Formats and Timing
      3. 7.4.3 Synchronization With the Digital Audio System
      4. 7.4.4 Mode Control
      5. 7.4.5 Parallel Hardware Control
    5. 7.5 Register Maps
      1. 7.5.1 Control Register Definitions (Software Mode Only)
      2. 7.5.2 Register Definitions
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Lowpass Filter and Differential-to-Single-Ended Converter for DAC Outputs
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Hardware Control Method
        2. 8.2.2.2 Audio Input
        3. 8.2.2.3 Audio Output
        4. 8.2.2.4 Master Clock
      3. 8.2.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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7 Detailed Description

7.1 Overview

The PCM1690 is a high-performance, multi-channel DAC targeted for consumer audio applications such as Blu-ray DVD players and HD DVD players, as well as home multi-channel audio applications (such as home theaters and A/V receivers). The PCM1690 consists of an eight-channel DAC. The DAC output type is fixed with a differential configuration. The PCM1690 supports 16-/20-/24-/32-bit linear PCM input data in I2S- and left-justified audio formats, and 24-bit linear PCM input data in right-justified, DSP, and TDM formats for various sampling frequencies from 8 kHz to 192 kHz. The TDM format is useful for saving bus line interface numbers for multi-channel audio data communication between the DAC and a digital audio processor. The PCM1690 offers three modes for device control: two-wire I2C software, three-wire SPI software, and hardware modes.

  • Audio data interface formats: I2S, LJ, RJ, DSP, TDM
  • Audio data word length: 16, 20, 24, 32 Bits
  • Audio data format: MSB first, twos complement

7.2 Functional Block Diagram

PCM1690 fbd_bas448.gif

7.3 Feature Description

7.3.1 Analog Outputs

The PCM1690 includes eight DACs, each with individual pairs of differential voltage outputs pins. The full-scale output voltage is (1.6 × VCC1) VPP at the differential output mode. A DC-coupled load is allowed in addition to an AC-coupled load if the load resistance conforms to the specification. These balanced outputs are each capable of driving 0.8 VCC1 (4 VPP) typical into a 5-kΩ, AC-coupled or 15-kΩ, DC-coupled load with VCC1 = +5 V. The internal output amplifiers for VOUT1 through VOUT8 are biased to the DC common voltage, equal to (0.5 × VCC1).

The output amplifiers include an RC continuous-time filter that helps to reduce the out-of-band noise energy present at the DAC outputs as a result of the noise shaping characteristics of the PCM1690 delta-sigma (ΔΣ) DACs. The frequency response of this filter is shown in the Analog Filter Characteristic (Figure 14). By itself, this filter is not enough to attenuate the out-of-band noise to an acceptable level for most applications. An external lowpass filter is required to provide sufficient out-of-band noise rejection. Further discussion of DAC post-filter circuits is provided in the Application Information section.

Table 1. Pin Assignments in Differential Output Mode

DIGITAL INPUT CHANNEL DIFFERENTIAL OUTPUT
DIN1 1 (DAC1) VOUT1+, VOUT1–
2 (DAC2) VOUT2+, VOUT2–
DIN2 3 (DAC3) VOUT3+, VOUT3–
4 (DAC4) VOUT4+, VOUT4–
DIN3 5 (DAC5) VOUT5+, VOUT5–
6 (DAC6) VOUT6+, VOUT6–
DIN4 7 (DAC7) VOUT7+, VOUT7–
8 (DAC8) VOUT8+, VOUT8–

7.3.2 Voltage Reference VCOM

The PCM1690 includes a pin for the common-mode voltage output, VCOM. This pin must be connected to the analog ground through a decoupling capacitor. This pin can also be used to bias external high-impedance circuits, if they are required.

7.3.3 System Clock Input

The PCM1690 requires an external system clock input applied at the SCKI input for DAC operation. The system clock operates at an integer multiple of the sampling frequency, or fS. The multiples supported in DAC operation include 128 fS, 192 fS, 256 fS, 384 fS, 512 fS, 768 fS, and 1152 fS. Details for these system clock multiples are shown in Table 2. Figure 1 and System Clock Timing Requirements show the SCKI timing requirements.

Table 2. System Clock Frequencies for Common Audio Sampling Rates

DEFAULT
SAMPLING
MODE
SAMPLING FREQUENCY SYSTEM CLOCK FREQUENCY (MHz)
fS (kHz) 128 fS 192 fS 256 fS 384 fS 512 fS 768 fS 1152 fS
Single rate 8 N/A N/A 2.0480 3.0720 4.0960 6.1440 9.2160
16 2.0480 3.0720 4.0960 6.1440 8.1920 12.2880 18.4320
32 4.0960 6.1440 8.1920 12.2880 16.3840 24.5760 36.8640
44.1 5.6448 8.4672 11.2896 16.9344 22.5792 33.8688 N/A
48 6.1440 9.2160 12.2880 18.4320 24.5760 36.8640 N/A
Dual rate 88.2 11.2896 16.9344 22.5792 33.8688 N/A N/A N/A
96 12.2880 18.4320 24.5760 36.8640 N/A N/A N/A
Quad rate 176.4 22.5792 33.8688 N/A N/A N/A N/A N/A
192 24.5760 36.8640 N/A N/A N/A N/A N/A

7.3.4 Sampling Mode

The PCM1690 supports three sampling modes (single rate, dual rate, and quad rate) in DAC operation. In single rate mode, the DAC operates at an oversampling frequency of x128 (except when SCKI = 128 fS and 192 fS). This mode is supported for sampling frequencies less than 50 kHz. In dual rate mode, the DAC operates at an oversampling frequency of x64; this mode is supported for sampling frequencies less than 100 kHz. In quad rate mode, the DAC operates at an oversampling frequency of x32. The sampling mode is automatically selected according to the ratio of system clock frequency and sampling frequency by default (that is, single rate for 512 fS, 768 fS, and 1152 fS; dual rate for 256 fS and 384 fS; and quad rate for 128 fS and 192 fS), but manual selection is also possible for specified combinations through the serial mode control register.

Table 3 and Figure 22 show the relation among the oversampling rate (OSR) of the digital filter and ΔΣ modulator, the noise-free shaped bandwidth, and each sampling mode setting.

Table 3. DAC Filter OSR, Modulator OSR, and Noise-Free Shaped Bandwidth for Each Sampling Mode

SAMPLING MODE REGISTER SETTING SYSTEM CLOCK FREQUENCY (xfS) NOISE-FREE SHAPED BANDWIDTH (kHz)(1) DIGITAL FILTER OSR MODULATOR OSR
fS = 48 kHz fS = 96 kHz fS = 192 kHz
Auto 512, 768, 1152 40 N/A N/A ×8 x128
256, 384 20 40 N/A x8 x64
128, 192(2) 10 20 40 x4 x32
Single 512, 768, 1152 40 N/A N/A x8 x128
256, 384 40 N/A N/A x8 x128
128, 192(2) 20 N/A N/A x4 x64
Dual 256, 384 20 40 N/A x8 x64
128, 192(2) 20 40 N/A x4 x64
Quad 128, 192(2) 10 20 40 x4 x32
(1) Bandwidth in which noise is shaped out.
(2) Quad mode filter characteristic is applied.
PCM1690 ai_mod_filt_char_bas448.gifFigure 22. ΔΣ Modulator and Digital Filter Characteristic

7.3.5 Reset Operation

The PCM1690 has both an internal power-on reset circuit and an external reset circuit. The sequences for both reset circuits are shown in Figure 23 and Figure 24. Figure 23 describes the timing at the internal power-on reset. Initialization is triggered automatically at the point where VDD exceeds 2.2 V typical, and the internal reset is released after 3846 SCKI clock cycles from power-on if RST is held high and SCKI is provided. VOUT from the DACs are forced to the VCOM level initially (that is, 0.5 × VCC1) and settle at a specified level according to the rising VCC. If synchronization among SCKI, BCK, and LRCK is maintained, VOUT provides an output that corresponds to DIN after 3846 SCKI clocks from power-on. If the synchronization is not held, the internal reset is not released, and both operating modes are maintained at reset and power-down states; after synchronization forms again, the DAC returns to normal operation with the previous sequences.

Figure 24 shows a timing diagram at the external reset. RST accepts an externally-forced reset with RST low, and provides a device reset and power-down state that achieves the lowest power dissipation state available in the PCM1690. If RST goes from high to low under synchronization among SCKI, BCK, and LRCK, the internal reset is asserted, all registers and memory are reset, and finally the PCM1690 enters into all power-down states. At the same time, VOUT is immediately forced into the AGND1 level. To begin normal operation again, toggle RST high; the same power-up sequence is performed as the power-on reset shown in Figure 23.

The PCM1690 does not require particular power-on sequences for VCC and VDD; it allows VDD on and then VCC on, or VCC on and then VDD on. From the viewpoint of the Absolute Maximum Ratings, however, simultaneous power-on is recommended for avoiding unexpected responses on VOUTx. Figure 23 shows the response for VCC on with VDD on.

PCM1690 ai_tim_por_bas448.gifFigure 23. Power-On-Reset Timing Requirements
PCM1690 ai_tim_ex_reset_bas448.gifFigure 24. External Reset Timing Requirements

7.3.6 Zero Flag

The PCM1690 has two ZERO flag pins (ZERO1 and ZERO2) that can be assigned to the combinations shown in Table 4. Zero flag combinations are selected through control register settings. If the input data of the left and right channel of all assigned channels remain at '0' for 1024 sampling periods (LRCK clock periods), the ZERO1/2 bits are set to a high level, logic '1' state. Furthermore, if the input data of any channels of assigned channels read '1', the ZERO1/2 are set to a low level, logic '0' state, immediately. Zero data detection is supported for 16-/20-/24-bit data width, but is not supported for 32-bit data width.

The active polarity of the zero flag output can be inverted through control register settings. The reset default is active high for zero detection. In parallel hardware control mode, ZERO1 and ZERO2 are fixed with combination A shown in Table 4.

Table 4. Zero Flag Outputs Combination

ZERO FLAG COMBINATION ZERO1 ZERO2
A DATA1, left channel DATA1, right channel
B DATA1–4 DATA1–4
C DATA4 DATA1–3
D DATA1 DATA2–4

7.3.7 AMUTE Control

The PCM1690 has an AMUTE control input, status output pins, and functionality. AMUTEI is the input control pin of the internal analog mute circuit. An AMUTEI low input causes the DAC output to cut-off from the digital input and forces it to the center level (0.5 VCC1). AMUTEO is the status output pin of the internal analog mute circuit. AMUTEO low indicates the analog mute control circuit is active because of a programmed condition (such as an SCKI halt, asynchronous detect, zero detect, or issue with the DAC disable command) that forces the DAC outputs to a center level. Because AMUTEI is not terminated internally and AMUTEO is an open-drain output, pull-ups by the appropriate resistors are required for proper operation.

Additionally, because the AMUTEI pin control and power-down control in register (OPEDA when high, PSMDA when low) do not function together, AMUTEI takes priority over power-down control. Therefore, power-down control is ignored during AMUTEI low, and AMUTEI low forces the DAC output to a center level (0.5 VCC1) even if the power-down control is asserted.

7.3.8 Three-Wire (SPI) Serial Control

The PCM1690 includes an SPI-compatible serial port that operates asynchronously with the audio serial interface. The control interface consists of MD/SDA/DEMP, MC/SCL/FMT, and MS/ADR0/RSV. MD is the serial data input to program the mode control registers. MC is the serial bit clock that shifts the data into the control port. MS is the select input to enable the mode control port.

7.3.9 Control Data Word Format

All single write operations via the serial control port use 16-bit data words. Figure 25 shows the control data word format. The first bit (fixed at '0') is for write controls; after the first bit are seven other bits, labeled ADR[6:0] that set the register address for the write operation. The eight least significant bits (LSBs), D[7:0] on MD, contain the data to be written to the register specified by ADR[6:0].

PCM1690 ai_op_ctrl_md_bas448.gifFigure 25. Control Data Word Format for MD

7.3.10 Register Write Operation

Figure 26 shows the functional timing diagram for single write operations on the serial control port. MS is held at a high state until a register is to be written. To start the register write cycle, MS is set to a low state. 16 clocks are then provided on MC, corresponding to the 16 bits of the control data word on MD. After the 16th clock cycle has been completed, MS is set high to latch the data into the indexed mode control register.

Also, the PCM1690 supports multiple write operations in addition to single write operations, which can be performed by sending the following N-times of the 8-bit register data after the first 16-bit register address and register data while keeping the MC clocks and MS at a low state. Closing a multiple write operation can be accomplished by setting MS to a high state.

PCM1690 ai_op_reg_wr_bas448.gif
1. X = don't care.
Figure 26. Register Write Operation

7.3.11 Two-Wire (I2C) Serial Control

The PCM1690 supports an I2C-compatible serial bus and data transmission protocol for fast mode configured as a slave device. This protocol is explained in the I2C specification 2.0.

The PCM1690 has a 7-bit slave address, as shown in Figure 27. The first five bits are the most significant bits (MSB) of the slave address and are factory-preset to 10011. The next two bits of the address byte are selectable bits that can be set by MS/ADR0/RSV and TEST/ADR1/RSV. A maximum of four PCM1690s can be connected on the same bus at any one time. Each PCM1690 responds when it receives its own slave address.

PCM1690 ai_slave_addy_bas448.gifFigure 27. Slave Address

7.3.12 Packet Protocol

A master device must control the packet protocol, which consists of a start condition, slave address with the read/write bit, data if a write operation is required, acknowledgment if a read operation is required, and stop condition. The PCM1690 supports both slave receiver and transmitter functions. Details about DATA for both write and read operations are described in Figure 28.

PCM1690 ai_tim_i2c_packet_bas448.gif
1. R/W: Read operation if '1'; write operation otherwise.
2. ACK: Acknowledgment of a byte if '0', not Acknowledgment of a byte if '1'.
3. DATA: Eight bits (byte); details are described in the Write Operation and Read Operation sections.
Figure 28. I2C Packet Control Protocol

7.3.13 Write Operation

The PCM1690 supports a receiver function. A master device can write to any PCM1690 register using single or multiple accesses. The master sends a PCM1690 slave address with a write bit, a register address, and the data. If multiple access is required, the address is that of the starting register, followed by the data to be transferred. When valid data are received, the index register automatically increments by one. When the register address reaches &h4F, the next value is &h40. When undefined registers are accessed, the PCM1690 does not send an acknowledgment. Figure 29 shows a diagram of the write operation. The register address and write data are in 8-bit, MSB-first format.

PCM1690 ai_op_wr_frame_bas448.gif
NOTE: M = Master device, S = Slave device, St = Start condition, W = Write, ACK = Acknowledge, and Sp = Stop condition.
Figure 29. Framework for Write Operation

7.3.14 Read Operation

A master device can read the registers of the PCM1690. The value of the register address is stored in an indirect index register in advance. The master sends the PCM1690 slave address with a read bit after storing the register address. Then the PCM1690 transfers the data that the index register points to. Figure 30 shows a diagram of the read operation.

PCM1690 ai_op_rd_frame_bas448.gif
NOTE: M = Master device, S = Slave device, St = Start condition, Sr = Repeated start condition, W = Write, R = Read, ACK = Acknowledge, NACK = Not acknowledge, and Sp = Stop condition.
NOTE: The slave address after the repeated start condition must be the same as the previous slave address.
Figure 30. Framework for Read Operation

7.3.15 Timing Requirements: SCL and SDA

A detailed timing diagram for SCL and SDA is shown in Figure 5.

7.4 Device Functional Modes

7.4.1 Audio Serial Port Operation

The PCM1690 audio serial port consists of six signals: BCK, LRCK, DIN1, DIN2, DIN3, and DIN4. BCK is a bit clock input. LRCK is a left/right word clock input or frame synchronization clock input. DIN1/2/3/4 are the audio data inputs for VOUT1–8.

7.4.2 Audio Data Interface Formats and Timing

The PCM1690 supports 10 audio data interface formats: 16-/20-/24-/32-bit I2S, 16-/20-/24-/32-bit left-justified, 24-bit right-justified, 16-bit right-justified, 24-bit left-justified mode DSP, 24-bit I2S mode DSP, 24-bit left-justified mode TDM, 24-bit I2S mode TDM, 24-bit left-justified mode high-speed TDM, and 24-bit I2S mode high-speed TDM. In the case of I2S, left-justified, and right-justified data formats, 64 BCKs, 48 BCKs, and 32 BCKs per LRCK period are supported; but 48 BCKs are limited in 192/384/768 fS SCKI, and 32 BCKs are limited in 16-bit right-justified only. In the case of TDM data format in single rate, BCK, LRCK, and DIN1 are used. In the case of TDM data format in dual rate, BCK, LRCK, and DIN1/2 are used. In the case of high-speed TDM format in dual rate, BCK, LRCK, and DIN1 are used. In the case of high-speed TDM format in quad rate, BCK, LRCK, and DIN1/2 are used. TDM format and high-speed TDM format are supported only at SCKI = 512 fS, 256 fS, 128 fS, and fBCK ≤ fSCKI. The audio data formats are selected by MC/SCL/FMT in hardware control mode and by control register settings in software control mode. All data must be in binary twos complement and MSB first.

Table 5 summarizes the applicable formats and describes the relationships among them and the respective restrictions with mode control. Figure 31 through Figure 37 show 10 audio interface data formats.

Table 5. Audio Data Interface Formats and Sampling Rate, Bit Clock, and System Clock Restrictions

CONTROL MODE FORMAT DATA BITS MAX LRCK FREQUENCY (fS) SCKI RATE (xfS) BCK RATE (xfS) APPLICABLE PINS
Software control I2S/Left-Justified 16/20/24/32(1) 192 kHz 128 to 1152(2) 64, 48 DIN1/2/3/4
Right-Justified 24, 16 192 kHz 128 to 1152(2) 64, 48, 32 (16 bit)(3) DIN1/2/3/4
I2S/Left-Justified DSP 24 192 kHz 128 to 768 64 DIN1/2/3/4
I2S/ Left-Justified TDM 24 48 kHz 256, 512 256 DIN1
24 96 kHz 128, 256 128 DIN1/2
High-Speed I2S/Left-Justified TDM 24 96 kHz 256 256 DIN1
24 192 kHz 128 128 DIN1/2
Hardware control I2S 16/20/24/32(1) 192 kHz 128 to 1152(2) 64, 48 DIN1/2/3/4
I2S TDM 24 48 kHz 512 256 DIN1
24 96 kHz 256 128 DIN1/2
(1) 32-bit data length is acceptable only for BCK = 64 fS and when using I2S and Left-Justified format.
(2) 1152 fS is acceptable only for fS = 32 kHz, BCK = 64 fS, and when using I2S, Left-Justified, and 24-bit Right-Justified format.
(3) BCK = 32 fS is supported only for 16-bit data length.
PCM1690 ai_tim_audio_16-32_i2s_bas448.gif
N = 15/19/23/31, M = 14/18/22/30, and L = 13/17/21/29
Figure 31. Audio Data Format: 16-/20-/24-/32-Bit I2S
PCM1690 ai_tim_audio_16-32_lj_bas448.gif
N = 15/19/23/31, M = 14/18/22/30, and L = 13/17/21/29
Figure 32. Audio Data Format: 16-/20-/24-/32-Bit Left-Justified
PCM1690 ai_tim_audio_24_rj_bas448.gifFigure 33. Audio Data Format: 24-Bit Right-Justified
PCM1690 ai_tim_audio_16_rj_bas448.gifFigure 34. Audio Data Format: 16-Bit Right-Justified
PCM1690 ai_tim_audio_24_dsp_bas448.gifFigure 35. Audio Data Format: 24-Bit DSP Format
PCM1690 ai_tim_audio_24_tdm_bas448.gif
SCKI = 128 fS, 256 fS, and 512 fS Only
Figure 36. Audio Data Format: 24-Bit TDM Format
PCM1690 ai_tim_audio_24_hs_tdm_bas448.gif
SCKI = 128 fS and 256 fS Only
Figure 37. Audio Data Format: 24-Bit High-Speed TDM Format

7.4.3 Synchronization With the Digital Audio System

The PCM1690 operates under the system clock (SCKI) and the audio sampling rate (LRCK). Therefore, SCKI and LRCK must have a specific relationship. The PCM1690 does not need a specific phase relationship between the audio interface clocks (LRCK, BCK) and the system clock (SCKI), but does require a specific frequency relationship (ratiometric) between LRCK, BCK, and SCKI.

If the relationship between SCKI and LRCK changes more than ±2 BCK clocks because of jitter, sampling frequency change, etc., the DAC internal operation stops within 1/fS, and the analog output is forced into VCOM (0.5 VCC1) until re-synchronization between SCKI, LRCK, and BCK completes and then 38/fS (single, dual rate) or 29/fS (quad rate) passes. In the event the change is less than ±2 BCKs, re-synchronization does not occur, and this analog output control and discontinuity does not occur.

Figure 38 shows the DAC analog output during loss of synchronization. During undefined data periods, some noise may be generated in the audio signal. Also, the transition of normal to undefined data and undefined (or zero) data to normal data creates a discontinuity of data on the analog outputs, which then may generate some noise in the audio signal.

DAC outputs (VOUTx) hold the previous state if the system clock halts, but the asynchronous and re-synchronization processes will occur after the system clock resumes.

PCM1690 ai_tim_dac_sync_loss_bas448.gifFigure 38. DAC Outputs During Loss of Synchronization

7.4.4 Mode Control

The PCM1690 includes three mode control interfaces with two oversampling configurations, depending on the input state of the MODE pin, as shown in Table 6. The pull-up and pull-down resistors must each be less than 10 kΩ.

Table 6. Mode Control Selection

MODE MODE CONTROL INTERFACE
Tied to DGND, low Two-wire (I2C) serial control, selectable oversampling configuration
Left open Two-wire parallel control, auto mode oversampling configuration
Tied to VDD, high Three-wire (SPI) serial control, selectable oversampling configuration

The input state of the MODE pin is sampled at the moment of power-on, or during a low-to-high transition of the RST pin, with the system clock input. Therefore, input changes after reset are ignored until the next power-on or reset. From the mode control selection described in Table 6, the functions of four pins are changed, as shown in Table 7.

Table 7. Pin Functions for Interface Mode

PIN PIN ASSIGNMENTS
SPI I2C H/W
20 MD (input) SDA (input/output) DEMP (input)
21 MC (input) SCL (input) FMT (input)
22 MS (input) ADR0 (input) RSV (input, low)
23 Test (output, open) ADR1 (input) RSV (input, low)

In serial mode control, the actual mode control is performed by register writes (and reads) through the SPI- or I2C-compatible serial control port. In parallel mode control, two specific functions are controlled directly through the high/low control of two specific pins, as described in the following section.

7.4.5 Parallel Hardware Control

The functions shown in Table 8 and Table 9 are controlled by two pins, DEMP and FMT, in parallel hardware control mode. The DEMP pin controls the 44.1-kHz digital de-emphasis function of all eight channels. The FMT pin controls the audio interface format for all eight channels.

Table 8. DEMP Functionality

DEMP DESCRIPTION
Low De-emphasis off
High 44.1 kHz de-emphasis on

Table 9. FMT Functionality

FMT DESCRIPTION
Low 16-/20-/24-/32-bit I2S format
High 24-bit I2S mode TDM format

7.5 Register Maps

7.5.1 Control Register Definitions (Software Mode Only)

The PCM1690 has many user-programmable functions that are accessed via control registers, and are programmed through the SPI or I2C serial control port. Table 10 shows the available mode control functions along with reset default conditions and associated register address. Table 11 lists the register map.

Table 10. User-Programmable Mode Control Functions

FUNCTION RESET DEFAULT REGISTER LABEL
Mode control register reset Normal operation 64 MRST
System reset Normal operation 64 SRST
Analog mute function control Mute disabled 64 AMUTE[3:0]
Sampling mode selection Auto 64 SRDA[1:0]
Power-save mode selection Power save 65 PSMDA
Audio interface format selection I2S 65 FMTDA[3:0]
Operation control Normal operation 66 OPEDA[3:0]
Digital filter roll-off control Sharp roll-off 66 FLT[3:0]
Output phase selection Normal 67 REVDA[8:1]
Soft mute control Mute disabled 68 MUTDA[8:1]
Zero flag Not detected 69 ZERO[8:1]
Digital attenuation mode 0 dB to –63 dB, 0.5 dB step 70 DAMS
Digital de-emphasis function control Disabled 70 DEMP[1:0]
Zero flag function selection ZERO1: DIN1, left-channel 70 AZRO[1:0]
ZERO2: DIN1, right-channel
Zero flag polarity selection High for detection 70 ZREV
Digital attenuation level setting 0 dB, no attenuation 71–79 ATDAx[7:0]

Table 11. Register Map

ADR[6:0] DATA[7:0]
DEC HEX B7 B6 B5 B4 B3 B2 B1 B0
64 40 MRST SRST AMUTE3 AMUTE2 AMUTE1 AMUTE0 SRDA1 SRDA0
65 41 PSMDA RSV(1) RSV(1) RSV(1) FMTDA3 FMTDA2 FMTDA1 FMTDA0
66 42 OPEDA3 OPEDA2 OPEDA1 OPEDA0 FLT3 FLT2 FLT1 FLT0
67 43 REVDA8 REVDA7 REVDA6 REVDA5 REVDA4 REVDA3 REVDA2 REVDA1
68 44 MUTDA8 MUTDA7 MUTDA6 MUTDA5 MUTDA4 MUTDA3 MUTDA2 MUTDA1
69 45 ZERO8 ZERO7 ZERO6 ZERO5 ZERO4 ZERO3 ZERO2 ZERO1
70 46 DAMS RSV(1) DEMP1 DEMP0 RSV(1) AZRO1 AZRO0 ZREV
71 47 RSV(1) RSV(1) RSV(1) RSV(1) RSV(1) RSV(1) RSV(1) RSV(1)
72 48 ATDA17 ATDA16 ATDA15 ATDA14 ATDA13 ATDA12 ATDA11 ATDA10
73 49 ATDA27 ATDA26 ATDA25 ATDA24 ATDA23 ATDA22 ATDA21 ATDA20
74 4A ATDA37 ATDA36 ATDA35 ATDA34 ATDA33 ATDA32 ATDA31 ATDA30
75 4B ATDA47 ATDA46 ATDA45 ATDA44 ATDA43 ATDA42 ATDA41 ATDA40
76 4C ATDA57 ATDA56 ATDA55 ATDA54 ATDA53 ATDA52 ATDA51 ATDA50
77 4D ATDA67 ATDA66 ATDA65 ATDA64 ATDA63 ATDA62 ATDA61 ATDA60
78 4E ATDA77 ATDA76 ATDA75 ATDA74 ATDA73 ATDA72 ATDA71 ATDA70
79 4F ATDA87 ATDA86 ATDA85 ATDA84 ATDA83 ATDA82 ATDA81 ATDA80
(1) RSV must be set to '0'.

7.5.2 Register Definitions

Table 1. Register 64 (Hex 40)

DEC HEX B7 B6 B5 B4 B3 B2 B1 B0
64 40 MRST SRST AMUTE3 AMUTE2 AMUTE1 AMUTE0 SRDA1 SRDA0
MRST Mode control register reset
This bit sets the mode control register reset to the default value. Pop noise may be generated. Returning the MRST bit to '1' is unnecessary because it is automatically set to '1' after the mode control register is reset.
Default value = 1.
MRST Mode control register reset
0 Set default value
1 Normal operation (default)
SRST System reset
This bit controls the system reset, which includes the resynchronization between the system clock and sampling clock, and DAC operation restart. The mode control register is not reset and the PCM1789 does not go into a power-down state. Returning the SRST bit to '1' is unnecessary; it is automatically set to '1' after triggering a system reset.
Default value = 1.
SRST System reset
0 Resynchronization
1 Normal operation (default)
AMUTE[3:0] Analog mute function control
These bits control the enabling/disabling of each source event that triggers the analog mute control circuit.
Default value = 0000.
AMUTE Analog mute function control
xxx0 Disable analog mute control by SCKI halt
xxx1 Enable analog mute control by SCKI halt
xx0x Disable analog mute control by asynchronous detect
xx1x Enable analog mute control by asynchronous detect
x0xx Disable analog mute control by ZERO1 and ZERO2 detect
x1xx Enable analog mute control by ZERO1 and ZERO2 detect
0xxx Disable analog mute control by DAC disable command
1xxx Enable analog mute control by DAC disable command
SRDA[1:0] Sampling mode selection
These bits control the sampling mode of DAC operation. In Auto mode, the sampling mode is automatically set according to multiples between the system clock and sampling clock: single rate for 512 fS, 768 fS, and 1152 fS, dual rate for 256 fS or 384 fS, and quad rate for 128 fS and 192 fS.
Default value = 00.
SRDA Sampling mode selection
00 Auto (default)
01 Single rate
10 Dual rate
11 Quad rate

Table 2. Register 65 (Hex 41)

DEC HEX B7 B6 B5 B4 B3 B2 B1 B0
65 41 PSMDA RSV RSV RSV FMTDA3 FMTDA2 FMTDA1 FMTDA0
PSMDA Power-save mode selection
This bit selects the power-save mode for the OPEDA[3:0] function. When PSMDA = 0, OPEDA[3:0] controls the power-save mode and normal operation. When PSMDA = 1, OPEDA functions controls the DAC disable (not power-save mode) and normal operation.
Default value: 0.
PSMDA Power-save mode selection
0 Power-save enable mode (default)
1 Power-save disable mode
RSV Reserved
Reserved; do not use.
FMTDA[3:0] Audio interface format selection
These bits control the audio interface format for DAC operation. Details of the format, and any related restrictions with the system clock are described in the Audio Data Interface Formats and Timing section.
Default value: 0000 (16-/20-/24-/32-bit I2S format).
FMTDA Audio interface format selection
0000 16-/20-/24-/32-bit I2S format (default)
0001 16-/20-/24-/32-bit left-justified format
0010 24-bit right-justified format
0011 16-bit right-justified format
0100 24-bit I2S mode DSP format
0101 24-bit left-justified mode DSP format
0110 24-bit I2S mode TDM format
0111 24-bit left-justified mode TDM format
1000 24-bit high-speed I2S mode TDM format
1001 24-bit high-speed left-justified mode TDM format
101x Reserved
11xx Reserved
1 Slow roll-off

Table 3. Register 66 (Hex 42)

DEC HEX B7 B6 B5 B4 B3 B2 B1 B0
66 42 OPEDA3 OPEDA2 OPEDA1 OPEDA0 FLT3 FLT2 FLT1 FLT0
OPEDA[3:0] Operation control
These bits control the DAC operation mode. In operation disable mode, the DAC output is cut off from DIN and the internal DAC data are reset. If PSMDA = 1, the DAC output is forced into VCOM. IF PSMDA = 0, the DAC output is forced into AGND and the DAC goes into a power-down state. For normal operating mode, these bits must be '0'. The serial mode control is effective during operation disable mode.
Default value: 0000.
OPEDA Operation control
xxx0 DAC1/2 normal operation
xxx1 DAC1/2 operation disable with or without power save
xx0x DAC3/4 normal operation
xx1x DAC3/4 operation disable with or without power save
x0xx DAC5/6 normal operation
x1xx DAC5/6 operation disable with or without power save
0xxx DAC7/8 normal operation
1xxx DAC7/8 operation disable with or without power save
FLT[3:0] Digital filter roll-off control
These bits allow users to select the digital filter roll-off that is best suited to their applications. Sharp and slow filter roll-off selections are available. The filter responses for these selections are shown in the Typical Characteristics section of this data sheet.
Default value: 0000.
FLT Digital filter roll-off control
xxx0 DAC1/2 sharp roll-off
xxx1 DAC1/2 slow roll-off
xx0x DAC3/4 sharp roll-off
xx1x DAC3/4 slow roll-off
x0xx DAC5/6 sharp roll-off
x1xx DAC5/6 slow roll-off
0xxx DAC7/8 sharp roll-off
1xxx DAC7/8 slow roll-off

Table 4. Register 67 (Hex 43)

DEC HEX B7 B6 B5 B4 B3 B2 B1 B0
67 43 REVDA8 REVDA7 REVDA6 REVDA5 REVDA4 REVDA3 REVDA2 REVDA1
REVDA[8:1] Output phase selection
These bits are used to control the phase of DAC analog signal outputs.
Default value: 0000 0000.
REVDA Output phase selection
xxxx xxx0 DAC1 normal output
xxxx xxx1 DAC1 inverted output
xxxx xx0x DAC2 normal output
xxxx xx1x DAC2 inverted output
xxxx x0xx DAC3 normal output
xxxx x1xx DAC3 inverted output
xxxx 0xxx DAC4 normal output
xxxx 1xxx DAC4 inverted output
xxx0 xxxx DAC5 normal output
xxx1 xxxx DAC5 inverted output
xx0x xxxx DAC6 normal output
xx1x xxxx DAC6 inverted output
x0xx xxxx DAC7 normal output
x1xx xxxx DAC7 inverted output
0xxx xxxx DAC8 normal output
1xxx xxxx DAC8 inverted output

Table 5. Register 68 (Hex 44)

DEC HEX B7 B6 B5 B4 B3 B2 B1 B0
68 44 MUTDA8 MUTDA7 MUTDA6 MUTDA5 MUTDA4 MUTDA3 MUTDA2 MUTDA1
MUTDA[8:1] Soft Mute control
These bits are used to enable or disable the Soft Mute function for the corresponding DAC outputs, VOUT. The Soft Mute function is incorporated into the digital attenuators. When mute is disabled (MUTDA[8:1] = 0), the attenuator and DAC operate normally. When mute is enabled by setting MUTDA[8:1] = 1, the digital attenuator for the corresponding output is decreased from the current setting to infinite attenuation. By setting MUTDA[8:1] = 0, the attenuator is increased to the last attenuation level in the same manner as it is for decreasing levels. This configuration reduces pop and zipper noise during muting of the DAC output. This Soft Mute control uses the same resource of digital attenuation level setting. Mute control has priority over the digital attenuation level setting.
Default value: 0000 0000.
MUTDA Soft Mute control
xxxx xxx0 DAC1 Mute disabled
xxxx xxx1 DAC1 Mute enabled
xxxx xx0x DAC2 Mute disabled
xxxx xx1x DAC2 Mute enabled
xxxx x0xx DAC3 Mute disabled
xxxx x1xx DAC3 Mute enabled
xxxx 0xxx DAC4 Mute disabled
xxxx 1xxx DAC4 Mute enabled
xxx0 xxxx DAC5 Mute disabled
xxx1 xxxx DAC5 Mute enabled
xx0x xxxx DAC6 Mute disabled
xx1x xxxx DAC6 Mute enabled
x0xx xxxx DAC7 Mute disabled
x1xx xxxx DAC7 Mute enabled
0xxx xxxx DAC8 Mute disabled
1xxx xxxx DAC8 Mute enabled

Table 6. Register 69 (Hex 45)

DEC HEX B7 B6 B5 B4 B3 B2 B1 B0
69 45 ZERO8 ZERO7 ZERO6 ZERO5 ZERO4 ZERO3 ZERO2 ZERO1
ZERO[8:1] Zero flag (read-only)
These bits indicate the present status of the zero detect circuit for each DAC channel; these bits are read-only.
ZERO Zero flag
xxxx xxx0 DAC1 zero input not detected
xxxx xxx1 DAC1 zero input detected
xxxx xx0x DAC2 zero input not detected
xxxx xx1x DAC2 zero input detected
xxxx x0xx DAC3 zero input not detected
xxxx x1xx DAC3 zero input detected
xxxx 0xxx DAC4 zero input not detected
xxxx 1xxx DAC4 zero input detected
xxx0 xxxx DAC5 zero input not detected
xxx1 xxxx DAC5 zero input detected
xx0x xxxx DAC6 zero input not detected
xx1x xxxx DAC6 zero input detected
x0xx xxxx DAC7 zero input not detected
x1xx xxxx DAC7 zero input detected
0xxx xxxx DAC8 zero input not detected
1xxx xxxx DAC8 zero input detected

Table 7. Register 70 (Hex 46)

DEC HEX B7 B6 B5 B4 B3 B2 B1 B0
70 46 DAMS RSV DEMP1 DEMP0 RSV AZRO1 AZRO0 ZREV
DAMS Digital attenuation mode
This bit selects the attenuation mode.
Default value: 0.
DAMS Digital attenuation mode
0 Fine step: 0.5-dB step for 0 dB to –63 dB range (default)
1 Wide range: 1-dB step for 0 dB to –100 dB range
RSV Reserved
Reserved; do not use.
DEMP[1:0] Digital de-emphasis function/sampling rate control
These bits are used to disable or enable the various sampling frequencies of the digital de-emphasis function.
Default value: 00.
DEMP Digital de-emphasis function/sampling rate control
00 Disable (default)
01 48 kHz enable
10 44.1 kHz enable
11 32 kHz enable
AZRO[1:0] Zero flag channel combination selection
The AZRO[1:0] bits are used to select the zero flag channel combination for ZERO1 and ZERO2.
If the analog mute function control by ZERO flags is used, AZRO[1:0] must not be set '00'; otherwise, analog mute works even if the data of DATA2–4 are not zero.
Default value: 00B.
AZRO Zero flag combination selection
00 Combination A: ZERO1 = DATA1 left channel, ZERO2 = DATA1 right channel (default)
01 Combination B: ZERO1 = DATA1–4, ZERO2 = DATA1–4
10 Combination C: ZERO1 = DATA4, ZERO2 = DATA1–3
11 Combination D: ZERO1 = DATA1, ZERO2 = DATA2–4
ZREV Zero flag polarity selection
This bit controls the polarity of the zero flag pin.
Default value: 0.
ZREV Zero flag polarity selection
0 High for zero detect (default)
1 Low for zero detect

Table 8. Registers 71-79 (Hex 47-49, 4A-4F)

DEC HEX B7 B6 B5 B4 B3 B2 B1 B0
71 47 RSV RSV RSV RSV RSV RSV RSV RSV
72 48 ATDA17 ATDA16 ATDA15 ATDA14 ATDA13 ATDA12 ATDA11 ATDA10
73 49 ATDA27 ATDA26 ATDA25 ATDA24 ATDA23 ATDA22 ATDA21 ATDA20
74 4A ATDA37 ATDA36 ATDA35 ATDA34 ATDA33 ATDA32 ATDA31 ATDA30
75 4B ATDA47 ATDA46 ATDA45 ATDA44 ATDA43 ATDA42 ATDA41 ATDA40
76 4C ATDA57 ATDA56 ATDA55 ATDA54 ATDA53 ATDA52 ATDA51 ATDA50
77 4D ATDA67 ATDA66 ATDA65 ATDA64 ATDA63 ATDA62 ATDA61 ATDA60
78 4E ATDA77 ATDA76 ATDA75 ATDA74 ATDA73 ATDA72 ATDA71 ATDA70
79 4F ATDA87 ATDA86 ATDA85 ATDA84 ATDA83 ATDA82 ATDA81 ATDA80
RSV Reserved
Reserved; do not use.
ATDAx[7:0] Digital attenuation level setting
Where x = 1 to 8, corresponding to the DAC output (VOUTx).
Each DAC output (VOUT1 through VOUT8) has a digital attenuation function. The attenuation level can be set from 0 dB to R dB, in S-dB steps. Changes in attenuator levels are made by incrementing or decrementing one step (S dB) for every 8/fS time interval until the programmed attenuator setting is reached. Alternatively, the attenuation level can be set to infinite attenuation (or mute). R (Range) and S (Step) is –63 and 0.5 for DAMS = 0 and –100 and 1.0 for DAMS = 1, respectively. The DAMS bit is defined in Register 70 (46h). Table 12 shows attenuation levels for various settings.
The attenuation level for each channel can be set individually using the following formula:
Attenuation level (dB) = S × (ATDAx[7:0]DEC – 255)
where ATDAx[7:0]DEC = 0 through 255.
For ATDAx[7:0]DEC = 0 through 128 with DAMS = 0 or 0 through 154 with DAMS = 1, attenuation is set to infinite attenuation (mute).
Default value: 1111 1111.

Table 12. Attenuation Levels for Various Settings

ATDAx[7:0] ATTENUATION LEVEL SETTING
BINARY DECIMAL DAMS = 0 DAMS = 1
1111 1111 255 0 dB, no attenuation (default) 0 dB, no attenuation (default)
1111 1110 254 –0.5 dB –1 dB
1111 1101 253 –1.0 dB –2 dB
... ... ... ...
1001 1100 156 –45.9 dB –99 dB
1001 1011 155 –50.0 dB –100 dB
1001 1010 154 –50.5 dB Mute
... ... ... ...
1000 0010 130 –62.5 dB Mute
1000 0001 129 –63.0 dB Mute
0000 0000 128 Mute Mute
... ... ... ...
0000 0000 0 Mute Mute