ZHCSE82B June   2015  – October 2015 OPT8241

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Optical Characteristics
    9. 6.9 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Block
        1. 7.3.1.1 Serializer and LVDS Output Interface
        2. 7.3.1.2 Parallel CMOS Output Interface
      2. 7.3.2 Temperature Sensor
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Presence Detection for Industrial Safety
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Frequencies of Operation
          2. 8.2.1.2.2 Number of Sub-Frames and Quads
          3. 8.2.1.2.3 Field of View (FoV)
          4. 8.2.1.2.4 Lens
          5. 8.2.1.2.5 Integration Duty Cycle
          6. 8.2.1.2.6 Design Summary
        3. 8.2.1.3 Application Curve
      2. 8.2.2 People Counting and Locating
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Frequencies of Operation
          2. 8.2.2.2.2 Number of Sub-Frames and Quads
          3. 8.2.2.2.3 Field of View (FoV)
          4. 8.2.2.2.4 Lens
          5. 8.2.2.2.5 Integration Duty Cycle
          6. 8.2.2.2.6 Design Summary
        3. 8.2.2.3 Application Curve
      3. 8.2.3 People Locating and Identification
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
          1. 8.2.3.2.1 Frequencies of Operation
          2. 8.2.3.2.2 Number of Sub-Frames and Quads
          3. 8.2.3.2.3 Field of View (FoV)
          4. 8.2.3.2.4 Lens
          5. 8.2.3.2.5 Integration Duty Cycle
          6. 8.2.3.2.6 Design Summary
        3. 8.2.3.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 MIX Supply Decapacitors
      2. 10.1.2 LVDS Transmitters
      3. 10.1.3 Optical Centering
      4. 10.1.4 Image Orientation
      5. 10.1.5 Thermal Considerations
    2. 10.2 Layout Example
    3. 10.3 Mechanical Assembly Guidelines
      1. 10.3.1 Board-Level Reliability
      2. 10.3.2 Handling
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

NBN Package
COG-78
Top View (Representative, Not to Scale)
OPT8241 po_sbas704.gif

Pin Functions

PIN FUNCTION I/O BANK DESCRIPTION
NAME NO.
AVDD D3, G17 Power 1.8-V analog VDD
AVDD_PLL A18 Power 1.8-V PLL VDD
AVDDH A17 Power 3.3-V analog VDD
AVSS E3, H3, H17 GND Analog ground
AVSS_PLL F17 GND PLL GND
CLKOUT M5 O IOVDD Parallel data clock output
CMOS[0] M13 O IOVDD Parallel data output bit 0
CMOS[1] M12 O IOVDD Parallel data output bit 1
CMOS[2] M11 O IOVDD Parallel data output bit 2
CMOS[3] M10 O IOVDD Parallel data output bit 3
CMOS[4] M9 O IOVDD Parallel data output bit 4
CMOS[5] M8 O IOVDD Parallel data output bit 5
CMOS[6] M7 O IOVDD Parallel data output bit 6
CMOS[7] M6 O IOVDD Parallel data output bit 7
CMOS[8] M4 O IOVDD Parallel data output bit 8
CMOS[9] M3 O IOVDD Parallel data output bit 9
CMOS[10] M2 O IOVDD Parallel data output bit 10
CMOS[11] L3 O IOVDD Parallel data output bit 11
CMOS[12] L1 O IOVDD Parallel data output bit 12
CMOS[13] K1 O IOVDD Parallel data output bit 13
CMOS[14] J1 O IOVDD Parallel data output bit 14
CMOS[15] K3 O IOVDD Parallel data output bit 15
DCLKM L19 O LVDS Negative LVDS bit clock
DCLKP M18 O LVDS Positive LVDS bit clock
DEMOD_CLK C19 I IOVDD Demodulation clock input (optional).
This pin has a weak internal pulldown resistor.
DIFF0_M M17 O LVDS Negative LVDS DIFF0 data pin
DIFF0_P M16 O LVDS Positive LVDS DIFF0 data pin
DIFF1_M K19 O LVDS Negative LVDS DIFF1 data pin
DIFF1_P L17 O LVDS Positive LVDS DIFF1 data pin
DVDD H19 Power 1.8-V digital VDD
DVDDH A14 Power 3.3-V digital VDD
DVSS G19 GND Digital GND
GND A4, A7, A8, A11, A15 GND Ground
GPO[0] A2 O IOVDD General-purpose output
GPO[1] B1 O IOVDD General-purpose output
HD_QD D1 O IOVDD Quad-frame line sync output
ILLUM_EN A16 O DVDDH Illumination enable
ILLUM_N A13 O DVDDH Illumination modulation signal; active low
ILLUM_P A12 O DVDDH Illumination modulation signal; active high
IOVDD H1, F19 Power 1.8-V to 3.3-V IOVDD
IOVSS G1 GND I/O GND
MCLK B19 I IOVDD Main clock input for TG.
This pin has a weak internal pulldown resistor.
NC A1, A19, C17, M1, M19 NC No connection
PCLK_M M15 O LVDS Negative LVDS pixel clock
PCLK_P M14 O LVDS Positive LVDS pixel clock
PVDD E17 Power 3.3-V pixel VDD
QPORT E19 I/O IOVDD Debug port.
Pullup with an external 1-kΩ resistor to IOVDD instead.
REFM F3 Analog In Connect REFM to GND
REFP G3 Analog Out ADC reference; connect a 10-nF capacitor close to REFM and REFP.
RFU D17 RFU Reserved for future use
RSTZ C3 I IOVDD Sensor reset input. This pin has a weak internal pullup resistor.
SCL B3 I IOVDD Clock I2C slave interface
SDATA A3 I/O IOVDD Data I2C slave interface
SUB_BIAS B17 Power Substrate bias
SUM_M J19 O LVDS Negative LVDS sum data
SUM_P K17 O LVDS Positive LVDS sum data
TP1 J17 O Debug pin 1, connect to a test pad on the board
TP2 D19 O Debug pin 2, connect to a test pad on the board
VD_FR F1 O IOVDD Frame sync output
VD_IN C1 I IOVDD Frame sync input (optional)
VD_QD E1 O IOVDD Quad-frame sync output
VD_SF J3 O Sub-frame sync output
VMIXH A5, A6, A9, A10 Power Mix driver power