ZHCSGM4C August   2017  – October 2023 OPA838

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: VS = 5 V
    6. 7.6 Electrical Characteristics: VS = 3 V
    7. 7.7 Typical Characteristics: VS = 5 V
    8. 7.8 Typical Characteristics: VS = 3 V
    9. 7.9 Typical Characteristics: Over Supply Range
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Common-Mode Voltage Range
      2. 8.3.2 Output Voltage Range
      3. 8.3.3 Power-Down Operation
      4. 8.3.4 Trade-Offs in Selecting The Feedback Resistor Value
      5. 8.3.5 Driving Capacitive Loads
    4. 8.4 Device Functional Modes
      1. 8.4.1 Split-Supply Operation (±1.35 V to ±2.7 V)
      2. 8.4.2 Single-Supply Operation (2.7 V to 5.4 V)
      3. 8.4.3 Power Shutdown Operation
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Noninverting Amplifier
      2. 9.1.2 Inverting Amplifier
      3. 9.1.3 Output DC Error Calculations
      4. 9.1.4 Output Noise Calculations
    2. 9.2 Typical Applications
      1. 9.2.1 High-Gain Differential I/O Designs
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Transimpedance Amplifier
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 TINA-TI™ Simulation Model Features
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 接收文档更新通知
    4. 10.4 支持资源
    5. 10.5 Trademarks
    6. 10.6 静电放电警告
    7. 10.7 术语表
  12.   Mechanical, Packaging, and Orderable Information

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9.2.2.1 Design Requirements

To implement a controlled frequency response transimpedance design, set the transimpedance stage amplifier bandwidth higher than a controlled post RC filter. This allows variation in the source capacitance and amplifier gain bandwidth product with less overall bandwidth variation to the final output. In this example design:

  • Assume a nominal source capacitance value of 100 pF. This normally comes from the capacitance versus reverse bias plot for the photodiode. No reverse bias is illustrated in Figure 9-8, but the current source is typically a back biased diode with a negative supply on the anode and the cathode connected to the op amp inverting input. In this polarity, the signal current sinks into the diode and raises the op amp output voltage above ground.
  • For the best dc precision, add a matching resistor on the noninverting input to reduce the input bias current error to IOS × RF. This resistor adds to the input voltage noise; TI recommends bypassing that resistor with as large as a capacitor as required to roll off resistor noise. This capacitor has a relatively low frequency self resonance that interacts with the input stage and can impair stability. Add a small series 20‑Ω resistor from the capacitor into the noninverting input to de-Q the resonant source impedance without adding too much noise.
  • Set the feedback capacitor to achieve the desired frequency response shape.
  • Add a post RC filter to control the overall bandwidth to 1 MHz. In this example, a 2.2‑nF capacitor allows a low 73.2‑Ω series resistor. When driving a sampling ADC (like a SAR), this combination helps reduce the sampling glitch and speed settling time.