ZHCSE93 September   2015 OPA2171-EP

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Operating Characteristics
      2. 7.3.2 Phase-Reversal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Common-Mode Voltage Range
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Electrical Overstress
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Capacitive Load and Stability
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 社区资源
    2. 11.2 商标
    3. 11.3 静电放电警告
    4. 11.4 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range, unless otherwise noted(1)
MIN MAX UNIT
Supply voltage ±20 V
Signal input pins Voltage (V–) – 0.5 (V+) + 0.5 V
Current –10 10 mA
Output short circuit(2) Continuous
Junction temperature 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Short-circuit to ground, one amplifier per package.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Supply voltage (V+ – V–) 4.5 (±2.25) 36 (±18) V
Operating temperature, TJ –55 125 °C

6.4 Thermal Information

THERMAL METRIC(1) OPA2171-EP UNIT
DCU (VSSOP)
8 PINS
RθJA Junction-to-ambient thermal resistance 175.2 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 74.9 °C/W
RθJB Junction-to-board thermal resistance 22.2 °C/W
ψJT Junction-to-top characterization parameter 1.6 °C/W
ψJB Junction-to-board characterization parameter 22.8 °C/W
RθJC(bot) Junction-to-case(bottom) thermal resistance N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

at TJ = 25°C, VS = 2.7 to 36 V, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
Input offset voltage VOS 0.25 ±1.8 mV
Over temperature TJ = –55°C to 125°C 0.3 ±2 mV
Drift dVOS/dT TJ = –55°C to 125°C 0.3 µV/°C
vs power supply PSRR VS = 4 to 36 V, TA = –55°C to 125°C 1 ±5 µV/V
Channel separation, dc dc 5 µV/V
INPUT BIAS CURRENT
Input bias current IB ±8 ±15 pA
Over temperature TJ = –55°C to 125°C ±4 nA
Input offset current IOS ±4 pA
Over temperature TJ = –55°C to 125°C ±4 nA
NOISE
Input voltage noise ƒ = 0.1 to 10 Hz 3 µVPP
Input voltage noise density en ƒ = 100 Hz 25 nV/√Hz
ƒ = 1 kHz 14 nV/√Hz
INPUT VOLTAGE
Common-mode voltage range(1) VCM (V–) – 0.1 V (V+) – 2 V V
Common-mode rejection ratio CMRR VS = ±2 V, (V–) – 0.1 V < VCM < (V+) – 2 V,
TJ = –55°C to 125°C		 87 104 dB
VS = ±18 V, (V–) – 0.1 V < VCM < (V+) – 2 V,
TJ = –55°C to 125°C		 104 120 dB
INPUT IMPEDANCE
Differential 100 || 3 MΩ || pF
Common-mode 6 || 3 1012Ω || pF
OPEN-LOOP GAIN
Open-loop voltage gain AOL VS = 4 to 36 V, (V–) + 0.35 V < VO < (V+) – 0.35 V, TJ = –55°C to 125°C 110 130 dB
FREQUENCY RESPONSE
Gain bandwidth product GBP 3.0 MHz
Slew rate SR G = +1 1.5 V/µs
Settling time tS To 0.1%, VS = ±18 V, G = +1, 10-V step 6 µs
To 0.01% (12 bit), VS = ±18 V, G = +1, 10-V step 10 µs
Overload recovery time VIN × Gain > VS 2 µs
Total harmonic distortion + noise THD+N G = +1, ƒ = 1kHz, VO = 3VRMS 0.0002%
OUTPUT
Voltage output swing from rail VO VS = 5 V, RL = 10 kΩ 30 mV
Over temperature RL = 10 kΩ, AOL ≥ 110 dB,
TJ = –55°C to 125°C		 (V–) + 0.35 (V+) – 0.35 V
Short-circuit current ISC +25/–35 mA
Capacitive load drive CLOAD See Typical Characteristics pF
Open-loop output resistance RO ƒ = 1 MHz, IO = 0 A 150 Ω
POWER SUPPLY
Specified voltage range VS 2.7 36 V
Quiescent current per amplifier IQ IO = 0 A 475 595 µA
Over temperature IO = 0 A, TJ = –55°C to 125°C 650 µA
TEMPERATURE
Operating temperature TJ –55 125 °C
(1) The input range can be extended beyond (V+) – 2 V up to V+. See Typical Characteristics and Application and Implementation for additional information.

6.6 Typical Characteristics

Table 1. Characteristic Performance Measurements

DESCRIPTION FIGURE
Offset Voltage Production Distribution Figure 1
Offset Voltage Drift Distribution Figure 2
Offset Voltage vs Temperature Figure 3
Offset Voltage vs Common-Mode Voltage Figure 4
Offset Voltage vs Common-Mode Voltage (Upper Stage) Figure 5
Offset Voltage vs Power Supply Figure 6
IB and IOS vs Common-Mode Voltage Figure 7
Input Bias Current vs Temperature Figure 8
Output Voltage Swing vs Output Current (Maximum Supply) Figure 9
CMRR and PSRR vs Frequency (Referred-to Input) Figure 10
CMRR vs Temperature Figure 11
PSRR vs Temperature Figure 12
0.1-Hz to 10-Hz Noise Figure 13
Input Voltage Noise Spectral Density vs Frequency Figure 14
THD+N Ratio vs Frequency Figure 15
THD+N vs Output Amplitude Figure 16
Quiescent Current vs Temperature Figure 17
Quiescent Current vs Supply Voltage Figure 18
Open-Loop Gain and Phase vs Frequency Figure 19
Closed-Loop Gain vs Frequency Figure 20
Open-Loop Gain vs Temperature Figure 21
Open-Loop Output Impedance vs Frequency Figure 22
Small-Signal Overshoot vs Capacitive Load (100-mV Output Step) Figure 23, Figure 24
No Phase Reversal Figure 25
Positive Overload Recovery Figure 26
Negative Overload Recovery Figure 27
Small-Signal Step Response (100 mV) Figure 28, Figure 29
Large-Signal Step Response Figure 30, Figure 31
Large-Signal Settling Time (10-V Positive Step) Figure 32
Large-Signal Settling Time (10-V Negative Step) Figure 33
Short-Circuit Current vs Temperature Figure 34
Maximum Output Voltage vs Frequency Figure 35
Channel Separation vs Frequency Figure 36
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
OPA2171-EP tc_histo_voff_bos516.gif
Figure 1. Offset Voltage Production Distribution
OPA2171-EP tc_vo-tmp_bos516.gif
Figure 3. Offset Voltage vs Temperature
OPA2171-EP tc_vos-vcm_upper_bos516.gif
Figure 5. Offset Voltage vs Common-Mode Voltage (Upper Stage)
OPA2171-EP tc_ib_ios-vcm_bos516.gif
Figure 7. IB and IOS vs Common-Mode Voltage
OPA2171-EP tc_vo_swing-io_bos516.gif
Figure 9. Output Voltage Swing vs Output Current (Maximum Supply)
OPA2171-EP tc_cmrr-tmp_bos516.gif
Figure 11. CMRR vs Temperature
OPA2171-EP tc_noise_bos516.gif
Figure 13. 0.1-Hz to 10-Hz Noise
OPA2171-EP tc_thdn-frq_bos516.gif
Figure 15. THD+N Ratio vs Frequency
OPA2171-EP tc_iq-tmp_bos516.gif
Figure 17. Quiescent Current vs Temperature
OPA2171-EP tc_g_ph-frq_bos516.gif
Figure 19. Open-Loop Gain and Phase vs Frequency
OPA2171-EP tc_g-tmp_bos516.gif
Figure 21. Open-Loop Gain vs Temperature
OPA2171-EP tc_sm_oshoot-cl_pos_bos516.gif
Figure 23. Small-Signal Overshoot vs Capacitive Load (100-mV Output Step)
OPA2171-EP tc_no_phase_bos516.gif
Figure 25. No Phase Reversal
OPA2171-EP tc_neg_oload_bos516.gif
Figure 27. Negative Overload Recovery
OPA2171-EP tc_sm_step_neg_bos516.gif
Figure 29. Small-Signal Step Response (100 mV)
OPA2171-EP tc_lg_step_neg_bos516.gif
Figure 31. Large-Signal Step Response
OPA2171-EP tc_lg_t_neg_bos516.gif
Figure 33. Large-Signal Settling Time (10-V Negative Step)
OPA2171-EP tc_max_vo-frq_bos516.gif
Figure 35. Maximum Output Voltage vs Frequency
OPA2171-EP tc_histo_voff_drift_bos516.gif
Figure 2. Offset Voltage Drift Distribution
OPA2171-EP tc_vos-vcm_bos516.gif
Figure 4. Offset Voltage vs Common-Mode Voltage
OPA2171-EP tc_vos-vsupply_bos516.gif
Figure 6. Offset Voltage vs Power Supply
OPA2171-EP tc_ibias-tmp_bos516.gif
Figure 8. Input Bias Current vs Temperature
OPA2171-EP tc_cmrr_psrr-frq_bos516.gif
Figure 10. CMRR and PSRR vs Frequency (Referred-to Input)
OPA2171-EP tc_psrr-tmp_bos516.gif
Figure 12. PSRR vs Temperature
OPA2171-EP tc_noise_spec-frq_bos516.gif
Figure 14. Input Voltage Noise Spectral Density vs Frequency
OPA2171-EP tc_thdn-outamp_bos516.gif
Figure 16. THD+N vs Output Amplitude
OPA2171-EP tc_iq-vs_bos516.gif
Figure 18. Quiescent Current vs Supply Voltage
OPA2171-EP tc_cloop_g-frq_bos516.gif
Figure 20. Closed-Loop Gain vs Frequency
OPA2171-EP tc_oloop_imp-frq_bos516.gif
Figure 22. Open-Loop Output Impedance vs Frequency
OPA2171-EP tc_sm_oshoot-cl_neg_bos516.gif
Figure 24. Small-Signal Overshoot vs Capacitive Load (100-mV Output Step)
OPA2171-EP tc_pos_oload_bos516.gif
Figure 26. Positive Overload Recovery
OPA2171-EP tc_sm_step_pos_bos516.gif
Figure 28. Small-Signal Step Response (100 mV)
OPA2171-EP tc_lg_step_pos_bos516.gif
Figure 30. Large-Signal Step Response
OPA2171-EP tc_lg_t_pos_bos516.gif
Figure 32. Large-Signal Settling Time (10-V Positive Step)
OPA2171-EP tc_isc-tmp_bos516.gif
Figure 34. Short-Circuit Current vs Temperature
OPA2171-EP tc_ch_sep-frq_bos516.gif
Figure 36. Channel Separation vs Frequency