ZHCS509E November 2011 – June 2018 OPA180 , OPA2180 , OPA4180
PRODUCTION DATA.
DAC: For convenience, devices with an external reference option or devices with accessible internal references are desirable in this application because the reference creates an offset. The DAC selection in this design must primarily be based on DC error contributions typically described by offset error, gain error, and integral nonlinearity error. Occasionally, additional specifications are provided that summarize end-point errors of the DAC typically called zero-code and full-scale errors. For AC applications, slew rate and settling time may require additional consideration.
Amplifier: Amplifier input offset voltage (VIO) is a key consideration for this design. VIO of an operational amplifier is a typical data sheet specification, but in-circuit performance is also affected by drift over temperature, the common-mode rejection ratio (CMRR), and power-supply rejection ratio (PSRR); thus consideration should be given to these parameters as well. For ac operation, additional considerations should be made concerning slew rate and settling time. Input bias current (IIB) can also be a factor, but typically the resistor network is implemented with sufficiently small resistor values that the effects of input bias current are negligible.
Passive: Resistor matching for the op-amp resistor network is critical for the success of this design; components with tight tolerances must be selected. For this design, 0.1% resistor values are implemented, but this constraint may be adjusted based on application-specific design goals. Resistor matching contributes to offset error and gain error in this design; see Bipolar ±10V Analog Output from a Unipolar Voltage Output DAC for further details. The tolerance of the RISOand CCOMP stability components is not critical, and 1% components are acceptable.