ZHCSJA6B January   2019  – December 2021 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. 功能方框图
  5. Revision History
  6. Device Comparison
    1. 6.1 Related Products
  7. Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Pin Attributes
    3. 7.3 Signal Descriptions
    4. 7.4 Pin Multiplexing
    5. 7.5 Buffer Type
    6. 7.6 Connection of Unused Pins
  8. Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5  Typical Characteristics, Active Mode Supply Currents
    6. 8.6  Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
    7. 8.7  Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 8.8  Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    9. 8.9  Low-Power Mode (LPMx.5) Supply Currents (Into VCC) Excluding External Current
    10. 8.10 Typical Characteristics, Low-Power Mode Supply Currents
    11. 8.11 Current Consumption per Module
    12. 8.12 Thermal Resistance Characteristics
    13. 8.13 Timing and Switching Characteristics
      1. 8.13.1  Power Supply Sequencing
        1. 8.13.1.1 Brownout and Device Reset Power Ramp Requirements
        2. 8.13.1.2 SVS
      2. 8.13.2  Reset Timing
        1. 8.13.2.1 Reset Input
      3. 8.13.3  Clock Specifications
        1. 8.13.3.1 Low-Frequency Crystal Oscillator, LFXT
        2. 8.13.3.2 High-Frequency Crystal Oscillator, HFXT
        3. 8.13.3.3 DCO
        4. 8.13.3.4 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        5. 8.13.3.5 Module Oscillator (MODOSC)
      4. 8.13.4  Wake-up Characteristics
        1. 8.13.4.1 Wake-up Times From Low-Power Modes and Reset
        2. 8.13.4.2 Typical Wake-up Charges
        3. 8.13.4.3 Typical Characteristics, Average LPM Currents vs Wake-up Frequency
      5. 8.13.5  Digital I/Os
        1. 8.13.5.1 Digital Inputs
        2. 8.13.5.2 Digital Outputs
        3. 8.13.5.3 Typical Characteristics, Digital Outputs
      6. 8.13.6  LEA
        1. 8.13.6.1 Low-Energy Accelerator (LEA) Performance
      7. 8.13.7  Timer_A and Timer_B
        1. 8.13.7.1 Timer_A
        2. 8.13.7.2 Timer_B
      8. 8.13.8  eUSCI
        1. 8.13.8.1 eUSCI (UART Mode) Clock Frequency
        2. 8.13.8.2 eUSCI (UART Mode) Switching Characteristics
        3. 8.13.8.3 eUSCI (SPI Master Mode) Clock Frequency
        4. 8.13.8.4 eUSCI (SPI Master Mode) Switching Characteristics
        5. 8.13.8.5 eUSCI (SPI Master Mode) Timing Diagrams
        6. 8.13.8.6 eUSCI (SPI Slave Mode) Switching Characteristics
        7. 8.13.8.7 eUSCI (SPI Slave Mode) Timing Diagrams
        8. 8.13.8.8 eUSCI (I2C Mode) Switching Characteristics
        9. 8.13.8.9 eUSCI (SPI Slave Mode) Timing Diagrams
      9. 8.13.9  Segment LCD Controller
        1. 8.13.9.1 LCD_C Recommended Operating Conditions
        2. 8.13.9.2 LCD_C Electrical Characteristics
      10. 8.13.10 ADC12_B
        1. 8.13.10.1 12-Bit ADC, Power Supply and Input Range Conditions
        2. 8.13.10.2 12-Bit ADC, Timing Parameters
        3. 8.13.10.3 12-Bit ADC, Linearity Parameters
        4. 8.13.10.4 12-Bit ADC, Dynamic Performance With External Reference
        5. 8.13.10.5 12-Bit ADC, Dynamic Performance With Internal Reference
        6. 8.13.10.6 12-Bit ADC, Temperature Sensor and Built-In V1/2
        7. 8.13.10.7 12-Bit ADC, External Reference
        8. 8.13.10.8 Temperature Sensor Typical Characteristics
      11. 8.13.11 Reference
        1. 8.13.11.1 REF, Built-In Reference
      12. 8.13.12 Comparator
        1. 8.13.12.1 Comparator_E
      13. 8.13.13 FRAM
        1. 8.13.13.1 FRAM Memory
      14. 8.13.14 USS
        1. 8.13.14.1 USS Recommended Operating Conditions
        2. 8.13.14.2 USS LDO
        3. 8.13.14.3 USSXTAL
        4. 8.13.14.4 USS HSPLL
        5. 8.13.14.5 USS SDHS
        6. 8.13.14.6 USS PHY Output Stage
        7. 8.13.14.7 USS PHY Input Stage, Multiplexer
        8. 8.13.14.8 USS_PGA
        9. 8.13.14.9 USS Bias Voltage Generator
      15. 8.13.15 Emulation and Debug
        1. 8.13.15.1 JTAG and Spy-Bi-Wire Interface
  9. Detailed Description
    1. 9.1  Overview
    2. 9.2  CPU
    3. 9.3  Ultrasonic Sensing Solution (USS_A)
    4. 9.4  Low-Energy Accelerator (LEA) for Signal Processing
    5. 9.5  Operating Modes
      1. 9.5.1 Peripherals in Low-Power Modes
      2. 9.5.2 Idle Currents of Peripherals in LPM3 and LPM4
    6. 9.6  Interrupt Vector Table and Signatures
    7. 9.7  Bootloader (BSL)
    8. 9.8  JTAG Operation
      1. 9.8.1 JTAG Standard Interface
      2. 9.8.2 Spy-Bi-Wire Interface
    9. 9.9  FRAM Controller A (FRCTL_A)
    10. 9.10 RAM
    11. 9.11 Tiny RAM
    12. 9.12 Memory Protection Unit (MPU) Including IP Encapsulation
    13. 9.13 Peripherals
      1. 9.13.1  Digital I/O
      2. 9.13.2  Oscillator and Clock System (CS)
      3. 9.13.3  Power-Management Module (PMM)
      4. 9.13.4  Hardware Multiplier (MPY)
      5. 9.13.5  Real-Time Clock (RTC_C)
      6. 9.13.6  Measurement Test Interface (MTIF)
      7. 9.13.7  Watchdog Timer (WDT_A)
      8. 9.13.8  System Module (SYS)
      9. 9.13.9  DMA Controller
      10. 9.13.10 Enhanced Universal Serial Communication Interface (eUSCI)
      11. 9.13.11 TA0, TA1, and TA4
      12. 9.13.12 TA2 and TA3
      13. 9.13.13 TB0
      14. 9.13.14 ADC12_B
      15. 9.13.15 USS_A
      16. 9.13.16 Comparator_E
      17. 9.13.17 CRC16
      18. 9.13.18 CRC32
      19. 9.13.19 AES256 Accelerator
      20. 9.13.20 True Random Seed
      21. 9.13.21 Shared Reference (REF)
      22. 9.13.22 LCD_C
      23. 9.13.23 Embedded Emulation
        1. 9.13.23.1 Embedded Emulation Module (EEM) (S Version)
        2. 9.13.23.2 EnergyTrace++ Technology
    14. 9.14 Input/Output Diagrams
      1. 9.14.1  Port Function Select Registers (PySEL1 , PySEL0)
      2. 9.14.2  Port P1 (P1.0 and P1.1) Input/Output With Schmitt Trigger
      3. 9.14.3  Port P1 (P1.2 to P1.5) Input/Output With Schmitt Trigger
      4. 9.14.4  Port P1 (P1.6 to P1.7) Input/Output With Schmitt Trigger
      5. 9.14.5  Port P2 (P2.0 to P2.1) Input/Output With Schmitt Trigger
      6. 9.14.6  Port P2 (P2.2 to P2.3) Input/Output With Schmitt Trigger
      7. 9.14.7  Port P2 (P2.4 to P2.5) Input/Output With Schmitt Trigger
      8. 9.14.8  Port P2 (P2.6 to P2.7) Input/Output With Schmitt Trigger
      9. 9.14.9  Port P3 (P3.0) Input/Output With Schmitt Trigger
      10. 9.14.10 Port P3 (P3.1) Input/Output With Schmitt Trigger
      11. 9.14.11 Port P3 (P3.2) Input/Output With Schmitt Trigger
      12. 9.14.12 Port P3 (P3.3) Input/Output With Schmitt Trigger
      13. 9.14.13 Port P3 (P3.4 to P3.5) Input/Output With Schmitt Trigger
      14. 9.14.14 Port P3 (P3.6 to P3.7) Input/Output With Schmitt Trigger
      15. 9.14.15 Port P4 (P4.0) Input/Output With Schmitt Trigger
      16. 9.14.16 Port P4 (P4.1 to P4.7) Input/Output With Schmitt Trigger
      17. 9.14.17 Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger
      18. 9.14.18 Port P6 (P6.0) Input/Output With Schmitt Trigger
      19. 9.14.19 Port P6 (P6.1 to P6.2) Input/Output With Schmitt Trigger
      20. 9.14.20 Port P6 (P6.3) Input/Output With Schmitt Trigger
      21. 9.14.21 Port P6 (P6.4) Input/Output With Schmitt Trigger
      22. 9.14.22 Port P6 (P6.5 and P6.7) Input/Output With Schmitt Trigger
      23. 9.14.23 Port P7 (P7.0) Input/Output With Schmitt Trigger
      24. 9.14.24 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
      25. 9.14.25 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
      26. 9.14.26 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
    15. 9.15 Device Descriptors (TLV)
    16. 9.16 Memory Map
      1. 9.16.1 Peripheral File Map
    17. 9.17 Identification
      1. 9.17.1 Revision Identification
      2. 9.17.2 Device Identification
      3. 9.17.3 JTAG Identification
  10. 10Applications, Implementation, and Layout
    1. 10.1 Device Connection and Layout Fundamentals
      1. 10.1.1  Power Supply and Bulk Capacitors
      2. 10.1.2  External Oscillator (HFXT and LFXT)
      3. 10.1.3  USS Oscillator (USSXT)
      4. 10.1.4  Transducer Connection to the USS Module
      5. 10.1.5  Charge Pump Control of Input Multiplexer
      6. 10.1.6  JTAG
      7. 10.1.7  Reset
      8. 10.1.8  Unused Pins
      9. 10.1.9  General Layout Recommendations
      10. 10.1.10 Do's and Don'ts
    2. 10.2 Peripheral- and Interface-Specific Design Information
      1. 10.2.1 ADC12_B Peripheral
        1. 10.2.1.1 Partial Schematic
        2. 10.2.1.2 Design Requirements
        3. 10.2.1.3 Detailed Design Procedure
        4. 10.2.1.4 Layout Guidelines
      2. 10.2.2 LCD_C Peripheral
        1. 10.2.2.1 Partial Schematic
        2. 10.2.2.2 Design Requirements
        3. 10.2.2.3 Detailed Design Procedure
        4. 10.2.2.4 Layout Guidelines
  11. 11Device and Documentation Support
    1. 11.1 Getting Started
    2. 11.2 Device Nomenclature
    3. 11.3 Tools and Software
    4. 11.4 Documentation Support
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 术语表
    9. 11.9 Export Control Notice
  12. 12Mechanical, Packaging, and Orderable Information

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Pin Attributes

Table 7-1 Pin Attributes
PIN NUMBER(1) SIGNAL NAME(1)(4) SIGNAL TYPE(2) BUFFER TYPE(3) POWER SOURCE(5) RESET STATE AFTER BOR(7)
FR6043, FR6041 FR5043, FR5041
1 1 AVCC1 P Power N/A
2 2 P2.2 I/O LVCMOS DVCC OFF
COUT O LVCMOS DVCC
UCA0CLK I/O LVCMOS DVCC
A14 I Analog DVCC
C14 I Analog DVCC
3 P2.3 I/O LVCMOS DVCC OFF
TA0.0 I/O LVCMOS DVCC
UCA0STE I/O LVCMOS DVCC
A15 I Analog DVCC
C15 I Analog DVCC
4 3 P1.0 I/O LVCMOS DVCC OFF
UCA1CLK I/O LVCMOS DVCC
TA1.0 I/O LVCMOS DVCC
A0 I Analog DVCC
C0 I Analog DVCC
VREF- O Analog DVCC
VeREF- I Analog DVCC
5 4 P1.1 I/O LVCMOS DVCC OFF
UCA1STE I/O LVCMOS DVCC
TA4.0 I/O LVCMOS DVCC
A1 I Analog DVCC
C1 I Analog DVCC
VREF+ O Analog DVCC
VeREF+ I Analog DVCC
6 5 AVSS2 P Power N/A
7 6 PJ.4 I/O LVCMOS DVCC OFF
LFXIN I Analog DVCC
8 7 PJ.5 I/O LVCMOS DVCC OFF
LFXOUT O Analog DVCC
9 8 AVSS3 P Power N/A
10 9 PJ.6 I/O LVCMOS DVCC
HFXIN I Analog DVCC
USSXT_BOUT O Analog DVCC
11 10 PJ.7 I/O LVCMOS DVCC OFF
HFXOUT O Analog DVCC
12 P2.4 I/O LVCMOS DVCC OFF
TA0CLK I LVCMOS DVCC
TB0CLK I LVCMOS DVCC
TA1CLK I LVCMOS DVCC
S24 O Analog DVCC
13 P2.6 I/O LVCMOS DVCC OFF
UCA0TXD O LVCMOS DVCC
UCA0SIMO I/O LVCMOS DVCC
TA1.2 I/O LVCMOS DVCC
TA1.2C I/O LVCMOS DVCC
S23 O Analog DVCC
14 P2.7 I/O LVCMOS DVCC OFF
UCA0RXD I LVCMOS DVCC
UCA0SOMI I/O LVCMOS DVCC
TA4.1 I/O LVCMOS DVCC
TA4.1C I/O LVCMOS DVCC
S22 O Analog DVCC
15 11 TEST I LVCMOS DVCC PD
SBWTCK I LVCMOS DVCC
16 12 RST I/O LVCMOS DVCC PU
NMI I LVCMOS DVCC
SBWTDIO I/O LVCMOS DVCC
17 13 PJ.0 I/O LVCMOS DVCC OFF
TDO O LVCMOS DVCC
UCA2CLK I/O LVCMOS DVCC
SRSCG1 O LVCMOS DVCC
DMAE0 I LVCMOS DVCC
C10 I Analog DVCC
18 14 PJ.1 I/O LVCMOS DVCC OFF
TDI I LVCMOS DVCC
TCLK I LVCMOS DVCC
UCA2STE I/O LVCMOS DVCC
SRSCG0 O LVCMOS DVCC
TA4CLK I LVCMOS DVCC
C11 I Analog DVCC
19 15 PJ.2 I/O LVCMOS DVCC OFF
TMS I LVCMOS DVCC
UCA2TXD O LVCMOS DVCC
UCA2SIMO I/O LVCMOS DVCC
SROSCOFF O LVCMOS DVCC
TB0OUTH I LVCMOS DVCC
C12 I Analog DVCC
20 16 PJ.3 I/O LVCMOS DVCC OFF
TCK I LVCMOS DVCC
UCA2RXD I LVCMOS DVCC
UCA2SOMI I/O LVCMOS DVCC
SRCPUOFF O LVCMOS DVCC
TB0.6 I/O LVCMOS DVCC
C13 I Analog DVCC
21 17 DVSS1 P Power N/A
22 18 DVCC1 P Power N/A
23 P2.5 I/O LVCMOS DVCC OFF
TA0.2 I/O LVCMOS DVCC
TA4.0 I/O LVCMOS DVCC
S21 O Analog DVCC
24 P3.0 I/O LVCMOS DVCC OFF
TB0.0 I/O LVCMOS DVCC
S20 O Analog DVCC
25 19 P1.2 I/O LVCMOS DVCC OFF
UCA1TXD O LVCMOS DVCC
UCA1SIMO I/O LVCMOS DVCC
TA1.0 I/O LVCMOS DVCC
A8 I Analog DVCC
C8 I Analog DVCC
26 20 P1.3 I/O LVCMOS DVCC OFF
UCA1RXD I LVCMOS DVCC
UCA1SOMI I/O LVCMOS DVCC
TA1.1 I/O LVCMOS DVCC
A9 I Analog DVCC
C9 I Analog DVCC
27 21 P2.0 I/O LVCMOS DVCC OFF
UCA1CLK I/O LVCMOS DVCC
UCA3TXD O LVCMOS DVCC
UCA3SIMO I/O LVCMOS DVCC
S19 O Analog DVCC
28 22 P2.1 I/O LVCMOS DVCC OFF
UCA1STE I/O LVCMOS DVCC
UCA3RXD I LVCMOS DVCC
UCA3SOMI I/O LVCMOS DVCC
S18 O Analog DVCC
29 23 P1.6 I/O LVCMOS DVCC OFF
UCA3STE I/O LVCMOS DVCC
UCB0SIMO I/O LVCMOS DVCC
UCB0SDA I/O LVCMOS DVCC
S17 O Analog DVCC
30 24 P1.7 I/O LVCMOS DVCC OFF
USSTRG I LVCMOS DVCC
UCA3CLK I/O LVCMOS DVCC
UCB0SOMI I/O LVCMOS DVCC
UCB0SCL I/O LVCMOS DVCC
S16 O Analog DVCC
31 25 P1.4 I/O LVCMOS DVCC OFF
TB0.4 I/O LVCMOS DVCC
UCA0STE I/O LVCMOS DVCC
A2 I Analog DVCC
C2 I Analog DVCC
32 26 P1.5 I/O LVCMOS DVCC OFF
TB0.5 I/O LVCMOS DVCC
UCB0CLK I/O LVCMOS DVCC
A3 I Analog DVCC
C3 I Analog DVCC
33 27 P3.1 I/O LVCMOS DVCC OFF
TA1CLK I LVCMOS DVCC
TB0.1 I/O LVCMOS DVCC
MTIF_OUT_IN I/O LVCMOS DVCC
34 28 P4.0 I/O LVCMOS DVCC OFF
RTCCLK O LVCMOS DVCC
TA4.1 O LVCMOS DVCC
MTIF_PIN_EN I LVCMOS DVCC
35 29 P4.1 I/O LVCMOS DVCC OFF
UCA0CLK I/O LVCMOS DVCC
TB0.4 I/O LVCMOS DVCC
UCA3RXD I LVCMOS DVCC
UCA3SOMI I/O LVCMOS DVCC
S15 O Analog DVCC
36 30 P4.2 I/O LVCMOS DVCC OFF
UCA0STE I/O LVCMOS DVCC
TB0.5 I/O LVCMOS DVCC
UCA3SIMO I/O LVCMOS DVCC
UCA3TXD O LVCMOS DVCC
S14 O Analog DVCC
37 31 P4.3 I/O LVCMOS DVCC OFF
UCA0TXD O LVCMOS DVCC
UCA0SIMO I/O LVCMOS DVCC
S13 O Analog DVCC
38 32 P4.4 I/O LVCMOS DVCC OFF
UCA0RXD I LVCMOS DVCC
UCA0SOMI I/O LVCMOS DVCC
S12 O Analog DVCC
39 P4.5 I/O LVCMOS DVCC OFF
TA0CLK I LVCMOS DVCC
TA1CLK I LVCMOS DVCC
S11 O Analog DVCC
40 P4.6 I/O LVCMOS DVCC OFF
TB0CLK I LVCMOS DVCC
TA4CLK I LVCMOS DVCC
S10 O Analog DVCC
41 33 DVSS2 P Power N/A
42 P4.7 I/O LVCMOS DVCC OFF
DMAE0 I LVCMOS DVCC
S9 O Analog DVCC
43 34 P5.0 I/O LVCMOS DVCC OFF
TB0.0 I/O LVCMOS DVCC
UCA2TXD O LVCMOS DVCC
UCA2SIMO I/O LVCMOS DVCC
S8 O Analog DVCC
44 35 P5.1 I/O LVCMOS DVCC OFF
TB0.1 O LVCMOS DVCC
UCA2RXD I LVCMOS DVCC
UCA2SOMI I/O LVCMOS DVCC
S7 O Analog DVCC
45 36 P5.2 I/O LVCMOS DVCC OFF
TB0.2 O LVCMOS DVCC
UCA2CLK I/O LVCMOS DVCC
S6 O Analog DVCC
46 37 P5.3 I/O LVCMOS DVCC OFF
TB0.3 O LVCMOS DVCC
UCA2STE I/O LVCMOS DVCC
S5 O Analog DVCC
47 38 P5.4 I/O LVCMOS DVCC OFF
TA0.0 I/O LVCMOS DVCC
UCB1CLK I/O LVCMOS DVCC
TA4.0 O LVCMOS DVCC
S4 O Analog DVCC
48 39 P5.5 I/O LVCMOS DVCC OFF
TA4.1 I/O LVCMOS DVCC
UCB1SIMO I/O LVCMOS DVCC
UCB1SDA I/O LVCMOS DVCC
S3 O Analog DVCC
49 40 P5.6 I/O LVCMOS DVCC OFF
TB0OUTH I LVCMOS DVCC
UCB1SOMI I/O LVCMOS DVCC
UCB1SCL I/O LVCMOS DVCC
S2 O Analog DVCC
50 41 P5.7 I/O LVCMOS DVCC OFF
TA0.2 I/O LVCMOS DVCC
UCB1STE I/O LVCMOS DVCC
S1 O Analog DVCC
51 42 P6.0 I/O LVCMOS DVCC OFF
TA0CLK I LVCMOS DVCC
COUT I LVCMOS DVCC
S0 O Analog DVCC
52 43 P6.4 I/O LVCMOS DVCC OFF
MCLK O LVCMOS DVCC
COM0 O Analog DVCC
53 44 P6.5 I/O LVCMOS DVCC OFF
SMCLK O LVCMOS DVCC
COM1 O Analog DVCC
S34 O Analog DVCC
54 45 P6.6 I/O LVCMOS DVCC OFF
ACLK O LVCMOS DVCC
COM2 O Analog DVCC
S31 O Analog DVCC
55 46 P7.0 I/O LVCMOS DVCC OFF
TA1.0 I/O LVCMOS DVCC
TA1.2 I/O LVCMOS DVCC
XPB0 O Analog 1.5 V
S30 O Analog DVCC
56 P6.1 I/O LVCMOS DVCC OFF
RTCCLK O LVCMOS DVCC
R03 I/O Analog DVCC
S33 O Analog DVCC
57 47 P6.2 I/O LVCMOS DVCC OFF
TB0CLK I LVCMOS DVCC
R13 I/O Analog DVCC
LCDREF I Analog -
S32 O Analog DVCC
58 48 DVSS3 P Power N/A
59 49 DVCC3 P Power N/A
60 P6.3 I/O LVCMOS DVCC OFF
COM7 O Analog DVCC
R23 I/O Analog DVCC
61 R33 I/O Analog DVCC -
LCDCAP I/O Analog DVCC
62 P6.7 I/O LVCMOS DVCC OFF
TA0.1 I/O LVCMOS DVCC
COM4 O Analog DVCC
S29 O Analog DVCC
63 P3.2 I/O LVCMOS DVCC OFF
TA1.1 I/O LVCMOS DVCC
COM5 O Analog DVCC
S28 O Analog DVCC
64 50 P3.3 I/O LVCMOS DVCC OFF
MCLK O LVCMOS DVCC
TB0.3 I/O LVCMOS DVCC
XPB1 O Analog 1.5 V
S25 O Analog DVCC
65 51 P3.4 I/O LVCMOS DVCC OFF
SMCLK O LVCMOS DVCC
COM6 O Analog DVCC
DMAE0 I LVCMOS DVCC
S27 O Analog DVCC
66 52 P3.5 I/O LVCMOS DVCC OFF
ACLK O LVCMOS DVCC
COM3 O Analog DVCC
COUT O LVCMOS DVCC
S26 O Analog DVCC
67 53 CH1_IN I Analog PVCC
68 54 CH1_OUT O Analog PVCC
69 55 PVSS P Power N/A
70 56 PVCC P Power N/A
71 57 PVCC P Power N/A
72 58 PVSS P Power N/A
73 59 CH0_OUT O Analog PVCC
74 60 CH0_IN I Analog PVCC
75 P3.6 I/O LVCMOS DVCC OFF
UCB1SIMO I/O LVCMOS DVCC
UCB1SDA I/O LVCMOS DVCC
TB0.6 I/O LVCMOS DVCC
USSXT_BOUT I/O LVCMOS DVCC
S35 O Analog DVCC
76 P3.7 I/O LVCMOS DVCC OFF
UCB1SOMI I/O LVCMOS DVCC
UCB1SCL I/O LVCMOS DVCC
TB0.2 I/O LVCMOS DVCC
TB0OUTH I LVCMOS DVCC
S36 O Analog DVCC
77 61 AVSS4 P Power N/A
78 62 USSXTIN(6) I Analog 1.5 V
79 63 USSXTOUT(6) O Analog 1.5 V
80 64 AVSS1 P Power N/A
The signal that is listed first for each pin is the reset default pin name.
Signal Types: I = Input, O = Output, I/O = Input or Output.
Buffer Types: LVCMOS, Analog, or Power (see Table 7-3 for details)
To determine the pin mux encodings for each pin, see Section 9.14.
The power source shown in this table is the I/O power source, which may differ from the module power source.
Do not connect the USSXTIN and USSXTOUT pins to AVCC or DVCC. USSXTIN does not support bypass mode, so do not drive an external clock to USSXTIN pin.
Reset States:
OFF = High impedance with Schmitt-trigger input and pullup or pulldown (if available) disabled
PU = Pullup is enabled
PD = Pulldown is enabled
N/A = Not applicable