SLVSGO3 December   2021 MCT8316Z-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings AUTO
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 SPI Timing Requirements
    7. 7.7 SPI Secondary Device Mode Timings
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Output Stage
      2. 8.3.2  PWM Control Mode (1x PWM Mode)
        1. 8.3.2.1 Analog Hall Input Configuration
        2. 8.3.2.2 Digital Hall Input Configuration
        3. 8.3.2.3 Asynchronous Modulation
        4. 8.3.2.4 Synchronous Modulation
        5. 8.3.2.5 Motor Operation
      3. 8.3.3  Device Interface Modes
        1. 8.3.3.1 Serial Peripheral Interface (SPI)
        2. 8.3.3.2 Hardware Interface
      4. 8.3.4  Step-Down Mixed-Mode Buck Regulator
        1. 8.3.4.1 Buck in Inductor Mode
        2. 8.3.4.2 Buck in Resistor mode
        3. 8.3.4.3 Buck Regulator with External LDO
        4. 8.3.4.4 AVDD Power Sequencing on Buck Regulator
        5. 8.3.4.5 Mixed mode Buck Operation and Control
      5. 8.3.5  AVDD Linear Voltage Regulator
      6. 8.3.6  Charge Pump
      7. 8.3.7  Slew Rate Control
      8. 8.3.8  Cross Conduction (Dead Time)
      9. 8.3.9  Propagation Delay
        1. 8.3.9.1 Driver Delay Compensation
      10. 8.3.10 Pin Diagrams
        1. 8.3.10.1 Logic Level Input Pin (Internal Pulldown)
        2. 8.3.10.2 Logic Level Input Pin (Internal Pullup)
        3. 8.3.10.3 Open Drain Pin
        4. 8.3.10.4 Push Pull Pin
        5. 8.3.10.5 Four Level Input Pin
        6. 8.3.10.6 Seven Level Input Pin
      11. 8.3.11 Active Demagnetization
        1. 8.3.11.1 Automatic Synchronous Rectification Mode (ASR Mode)
          1. 8.3.11.1.1 Automatic Synchronous Rectification in Commutation
          2. 8.3.11.1.2 Automatic Synchronous Rectification in PWM Mode
        2. 8.3.11.2 Automatic Asynchronous Rectification Mode (AAR Mode)
      12. 8.3.12 Cycle-by-Cycle Current Limit
        1. 8.3.12.1 Cycle by Cycle Current Limit with 100% Duty Cycle Input
      13. 8.3.13 Hall Comparators (Analog Hall Inputs)
      14. 8.3.14 Advance Angle
      15. 8.3.15 FGOUT Signal
      16. 8.3.16 Protections
        1. 8.3.16.1  VM Supply Undervoltage Lockout (NPOR)
        2. 8.3.16.2  AVDD Undervoltage Lockout (AVDD_UV)
        3. 8.3.16.3  BUCK Undervoltage Lockout (BUCK_UV)
        4. 8.3.16.4  VCP Charge Pump Undervoltage Lockout (CPUV)
        5. 8.3.16.5  Overvoltage Protections (OV)
        6. 8.3.16.6  Overcurrent Protection (OCP)
          1. 8.3.16.6.1 OCP Latched Shutdown (OCP_MODE = 00b)
          2. 8.3.16.6.2 OCP Automatic Retry (OCP_MODE = 01b)
          3. 8.3.16.6.3 OCP Report Only (OCP_MODE = 10b)
          4. 8.3.16.6.4 OCP Disabled (OCP_MODE = 11b)
        7. 8.3.16.7  Buck Overcurrent Protection
        8. 8.3.16.8  Motor Lock (MTR_LOCK)
          1. 8.3.16.8.1 MTR_LOCK Latched Shutdown (MTR_LOCK_MODE = 00b)
          2. 8.3.16.8.2 MTR_LOCK Automatic Retry (MTR_LOCK_MODE = 01b)
          3. 8.3.16.8.3 MTR_LOCK Report Only (MTR_LOCK_MODE= 10b)
          4. 8.3.16.8.4 MTR_LOCK Disabled (MTR_LOCK_MODE = 11b)
          5. 8.3.16.8.5 76
        9. 8.3.16.9  Thermal Warning (OTW)
        10. 8.3.16.10 Thermal Shutdown (OTS)
          1. 8.3.16.10.1 OTS FET
          2. 8.3.16.10.2 OTS (Non FET)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Functional Modes
        1. 8.4.1.1 Sleep Mode
        2. 8.4.1.2 Operating Mode
        3. 8.4.1.3 Fault Reset (CLR_FLT or nSLEEP Reset Pulse)
      2. 8.4.2 DRVOFF functionality
    5. 8.5 SPI Communication
      1. 8.5.1 Programming
        1. 8.5.1.1 SPI Format
    6. 8.6 Register Map
      1. 8.6.1 STATUS Registers
      2. 8.6.2 CONTROL Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Hall Sensor Configuration and Connection
      1. 9.2.1 Typical Configuration
      2. 9.2.2 Open Drain Configuration
      3. 9.2.3 Series Configuration
      4. 9.2.4 Parallel Configuration
    3. 9.3 Typical Applications
      1. 9.3.1 Three-Phase Brushless-DC Motor Control With Current Limit
        1. 9.3.1.1 Detailed Design Procedure
          1. 9.3.1.1.1 Motor Voltage
          2. 9.3.1.1.2 Using Active Demagnetization
          3. 9.3.1.1.3 Using Delay Compensation
          4. 9.3.1.1.4 Using the Buck Regulator
          5. 9.3.1.1.5 Power Dissipation and Junction Temperature Losses
        2. 9.3.1.2 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
      1. 11.3.1 Power Dissipation
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.5 Electrical Characteristics

TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES
IVMQ VM sleep mode current VVM > 6 V, nSLEEP = 0, TA = 25 °C 1.5 2.5 µA
nSLEEP = 0 2.5 5 µA
IVMS VM standby mode current
(Buck regulator disabled) 		 nSLEEP = 1, PWM = 0, SPI = 'OFF', BUCK_DIS = 1; 4 10 mA
VVM > 6 V, nSLEEP = 1, PWM = 0, SPI = 'OFF', TA = 25 °C, BUCK_DIS = 1;  4 5 mA
IVMS VM standby mode current
(Buck regulator enabled)		 VVM > 6 V, nSLEEP = 1, PWM = 0, SPI = 'OFF', IBK = 0, TA = 25 °C, BUCK_DIS = 0;  5 6 mA
nSLEEP = 1, PWM = 0, SPI = 'OFF', IBK = 0, BUCK_DIS = 0;  6 10 mA
IVM VM operating mode current
(Buck regulator disabled)		 VVM > 6 V, nSLEEP = 1, fPWM = 25 kHz, TA = 25 °C, BUCK_DIS = 1 10 13 mA
VVM > 6 V, nSLEEP = 1, fPWM = 200 kHz, TA = 25 °C, BUCK_DIS = 1 18 21 mA
 nSLEEP =1, fPWM = 25 kHz, BUCK_DIS = 1 11 15 mA
nSLEEP =1, fPWM = 200 kHz, BUCK_DIS = 1 17 24 mA
IVM VM operating mode current
(Buck regulator enabled)		 VVM > 6 V, nSLEEP = 1, fPWM = 25 kHz, TA = 25 °C, BUCK_DIS = 0; BUCK_PS_DIS = 0 11 13 mA
VVM > 6 V, nSLEEP = 1, fPWM = 200 kHz, TA = 25 °C, BUCK_DIS = 0; BUCK_PS_DIS = 0 19 22 mA
 nSLEEP =1, fPWM = 25 kHz, BUCK_DIS = 0; BUCK_PS_DIS = 0 12 16 mA
 nSLEEP =1, fPWM = 200 kHz, BUCK_DIS = 0; BUCK_PS_DIS = 0 18 27 mA
VAVDD Analog regulator voltage 0 mA ≤ IAVDD ≤ 30 mA; BUCK_PS_DIS = 0 3.1 3.3 3.465 V
IAVDD External analog regulator load 30 mA
VVCP Charge pump regulator voltage VCP with respect to VM 3.6 4.7 5.2 V
fCP Charge pump switching frequency 400 kHz
tPWM_LOW PWM low time required for motor lock detection 200 ms
tWAKE Wakeup time VVM > VUVLO, nSLEEP = 1 to outputs ready and nFAULT released 1 ms
tSLEEP Sleep Pulse time nSLEEP = 0 period to enter sleep mode 120 µs
tRST Reset Pulse time nSLEEP = 0 period to reset faults 20 40 µs
BUCK REGULATOR
VBK Buck regulator average voltage
(LBK = 47 µH, CBK = 22 µF)
(SPI Device)		 VVM > 6 V, 0 mA ≤ IBK ≤ 200 mA, BUCK_SEL = 00b 3.1 3.3 3.5 V
VVM > 6 V, 0 mA ≤ IBK ≤ 200 mA, BUCK_SEL = 01b 4.6 5.0 5.4 V
VVM > 6 V, 0 mA ≤ IBK ≤ 200 mA, BUCK_SEL = 10b 3.7 4.0 4.3 V
VVM > 6.7 V, 0 mA ≤ IBK ≤ 200 mA, BUCK_SEL = 11b 5.2 5.7 6.2 V
VVM < 6.0 V (BUCK_SEL = 00b, 01b, 10b) or VVM < 6.0 V (BUCK_SEL = 11b),  0 mA ≤ IBK ≤ 200 mA VVM–IBK*(RLBK+2)(1) V
VBK Buck regulator average voltage
(LBK = 22 µH, CBK = 22 µF)
(SPI Device)		 VVM  > 6 V, 0 mA ≤ IBK ≤ 50 mA, BUCK_SEL = 00b 3.1 3.3 3.5 V
VVM > 6 V, 0 mA ≤ IBK ≤ 50 mA, BUCK_SEL = 01b 4.6 5.0 5.4 V
VVM  > 6 V, 0 mA ≤ IBK ≤ 50 mA, BUCK_SEL = 10b 3.7 4.0 4.3 V
VVM  > 6.7 V, 0 mA ≤ IBK ≤ 50 mA, BUCK_SEL = 11b 5.2 5.7 6.2 V
VVM < 6.0 V (BUCK_SEL = 00b, 01b, 10b) or VVM < 6.0 V (BUCK_SEL = 11b),  0 mA ≤ IBK ≤ 50 mA VVM–IBK*(RLBK+2) (1) V
VBK Buck regulator average voltage
(RBK = 22 Ω, CBK = 22 µF)
(SPI Device)		 VVM  > 6 V, 0 mA ≤ IBK ≤ 40 mA, BUCK_SEL = 00b 3.1 3.3 3.5 V
VVM > 6 V, 0 mA ≤ IBK ≤ 40 mA, BUCK_SEL = 01b 4.6 5.0 5.4 V
VVM  > 6 V, 0 mA ≤ IBK ≤ 40 mA, BUCK_SEL = 10b 3.7 4.0 4.3 V
VVM  > 6.7 V, 0 mA ≤ IBK ≤ 40 mA, BUCK_SEL = 11b 5.2 5.7 6.2 V
VVM < 6.0 V (BUCK_SEL = 00b, 01b, 10b) or VVM < 6.0 V (BUCK_SEL = 11b),  0 mA ≤ IBK ≤ 40 mA VVM–IBK*(RBK+2)(1) V
VBK Buck regulator average voltage
(LBK = 47 µH, CBK = 22 µF)
(HW Device)		 VVM > 6 V, 0 mA ≤ IBK ≤ 200 mA, VSEL_BK pin tied to AGND   3.1 3.3 3.5 V
VVM > 6 V, 0 mA ≤ IBK ≤ 200 mA, VSEL_BK pin to Hi-Z 4.6 5.0 5.4
VVM > 6 V, 0 mA ≤ IBK ≤ 200 mA, VSEL_BK pin to 47 kΩ +/- 5% tied to AVDD 3.7 4.0 4.3
VVM > 6.7 V, 0 mA ≤ IBK ≤ 200 mA, VSEL_BK pin tied to AVDD 5.2 5.7 6.2
VVM < 6.0 V, 0 mA ≤ IBK ≤ 200 mA VVM–IBK*(RLBK+2)(1) V
VBK Buck regulator average voltage
(LBK = 22 µH, CBK = 22 µF)
(HW Device)		 VVM > 6 V, 0 mA ≤ IBK ≤ 50 mA, VSEL_BK pin tied to AGND   3.1 3.3 3.5 V
VVM > 6 V, 0 mA ≤ IBK ≤ 50 mA, VSEL_BK pin to Hi-Z 4.6 5.0 5.4 V
VVM > 6 V, 0 mA ≤ IBK ≤ 50 mA, VSEL_BK pin to 47 kΩ +/- 5% tied to AVDD 3.7 4.0 4.3 V
VVM > 6.7 V, 0 mA ≤ IBK ≤ 50 mA, VSEL_BK pin tied to AVDD 5.2 5.7 6.2 V
VVM < 6.0 V, 0 mA ≤ IBK ≤ 50 mA VVM–IBK*(RLBK+2)(1) V
VBK Buck regulator average voltage
(RBK = 22 Ω, CBK = 22 µF)
(HW Device)		 VVM > 6 V, 0 mA ≤ IBK ≤ 40 mA, VSEL_BK pin tied to AGND   3.1 3.3 3.5 V
VVM > 6 V, 0 mA ≤ IBK ≤ 40 mA, VSEL_BK pin to Hi-Z 4.6 5.0 5.4 V
VVM > 6 V, 0 mA ≤ IBK ≤ 40 mA, VSEL_BK pin to 47 kΩ +/- 5% tied to AVDD 3.7 4.0 4.3 V
VVM > 6.7 V, 0 mA ≤ IBK ≤ 40 mA, VSEL_BK pin tied to AVDD 5.2 5.7 6.2 V
VVM  < 6.0 V, 0 mA ≤ IBK ≤ 40 mA VVM–IBK*(RBK+2)(1) V
VBK_RIP Buck regulator ripple voltage VVM  > 6 V, 0 mA ≤ IBK ≤ 200 mA, Buck regulator with inductor, LBK = 47 uH, CBK = 22 µF –100 100 mV
VVM  > 6 V, 0 mA ≤ IBK ≤ 50 mA, Buck regulator with inductor, LBK = 22 uH, CBK = 22 µF –100 100 mV
VVM  > 6 V, 0 mA ≤ IBK ≤ 50 mA, Buck regulator with resistor; RBK = 22 Ω, CBK = 22 µF –100 100 mV
IBK External buck regulator load LBK = 47 uH, CBK = 22 µF, BUCK_PS_DIS = 1b 200 mA
LBK = 47 uH, CBK = 22 µF, BUCK_PS_DIS = 0b 200 – IAVDD mA
LBK = 22 uH, CBK = 22 µF, BUCK_PS_DIS = 1b 50 mA
LBK = 22 uH, CBK = 22 µF, BUCK_PS_DIS = 0b 50 – IAVDD mA
RBK = 22 Ω, CBK = 22 µF, BUCK_PS_DIS = 1b 40 mA
RBK = 22 Ω, CBK = 22 µF, BUCK_PS_DIS = 0b 40 – IAVDD mA
fSW_BK Buck regulator switching frequency  Regulation Mode 20 535 kHz
Linear Mode 20 535 kHz
VBK_UV Buck regulator undervoltage lockout
(SPI Device)		 VBK rising, BUCK_SEL = 00b 2.7 2.8 2.9 V
VBK falling, BUCK_SEL = 00b 2.5 2.6 2.7 V
VBK rising, BUCK_SEL = 01b 4.2 4.4 4.55 V
VBK falling, BUCK_SEL = 01b 4.0 4.2 4.35 V
VBK rising, BUCK_SEL = 10b 2.7 2.8 2.9 V
VBK falling, BUCK_SEL = 10b 2.5 2.6 2.7 V
VBK rising, BUCK_SEL = 11b 4.2 4.4 4.55 V
VBK falling, BUCK_SEL = 11b 4 4.2 4.35 V
VBK_UV Buck regulator undervoltage lockout
(HW Device)		 VBK rising, VSEL_BK pin tied to AGND 2.7 2.8 2.9 V
VBK falling, VSEL_BK pin tied to AGND 2.5 2.6 2.7 V
VBK rising, VSEL_BK pin to 47 kΩ +/- 5% tied to AVDD 4.3 4.4 4.5 V
VBK falling, VSEL_BK pin to 47 kΩ +/- 5% tied to AVDD 4.1 4.2 4.3 V
VBK rising, VSEL_BK pin to Hi-Z 2.7 2.8 2.9 V
VBK falling, VSEL_BK pin to Hi-Z 2.5 2.6 2.7 V
VBK rising, VSEL_BK pin tied to AVDD 4.2 4.4 4.55 V
VBK falling, VSEL_BK pin tied to AVDD 4.0 4.2 4.35 V
VBK_UV_HYS Buck regulator undervoltage lockout hysteresis Rising to falling threshold 90 200 320 mV
IBK_CL Buck regulator Current limit threshold
(SPI Device)		 BUCK_CL = 0b 360 600 900 mA
BUCK_CL = 1b 80 150 250 mA
IBK_CL Buck regulator Current limit threshold 
(HW Device)		 360 600 900 mA
IBK_OCP Buck regulator Overcurrent protection trip point 2 3 4 A
tBK_RETRY Overcurrent protection retry time 0.7 1 1.3 ms
LOGIC-LEVEL INPUTS (BRAKE, DIR, DRVOFF, nSLEEP, PWM, SCLK, SDI)
VIL Input logic low voltage 0 0.6 V
VIH Input logic high voltage Other Pins 1.5 5.5 V
nSLEEP 1.6 5.5 V
VHYS Input logic hysteresis Other PIns 180 300 420 mV
nSLEEP 95 250 420 mV
IIL Input logic low current VPIN (Pin Voltage) = 0 V –1 1 µA
IIH Input logic high current nSLEEP, VPIN (Pin Voltage) = 5 V 10 30 µA
Other pins, VPIN (Pin Voltage) = 5 V 30 75 µA
RPD Input pulldown resistance nSLEEP 150 200 300 kΩ
Other pins 70 100 130 kΩ
CID Input capacitance 30 pF
LOGIC-LEVEL INPUTS (nSCS)
VIL Input logic low voltage 0 0.6 V
VIH Input logic high voltage 1.5 5.5 V
VHYS Input logic hysteresis 180 300 420 mV
IIL Input logic low current VPIN (Pin Voltage) = 0 V 75 µA
IIH Input logic high current VPIN (Pin Voltage) = 5 V –1 25 µA
RPU Input pullup resistance 80 100 130 kΩ
CID Input capacitance 30 pF
FOUR-LEVEL INPUTS (SLEW, VSEL_BK)
VL1 Input mode 1 voltage Tied to AGND 0 0.2*AVDD V
VL2 Input mode 2 voltage Hi-Z 0.27*AVDD 0.5*AVDD 0.545*AVDD V
VL3 Input mode 3 voltage 47 kΩ +/- 5% tied to AVDD 0.606*AVDD 0.757*AVDD 0.909*AVDD V
VL4 Input mode 4 voltage Tied to AVDD 0.945*AVDD AVDD V
RPU Input pullup resistance To AVDD 70 100 130 kΩ
RPD Input pulldown resistance To AGND 70 100 130 kΩ
FOUR-LEVEL INPUTS (OCP/SR)
VL1 Input mode 1 voltage Tied to AGND 0 0.09*AVDD V
VL2 Input mode 2 voltage 22 kΩ ± 5% to AGND 0.12*AVDD 0.15*AVDD 0.2*AVDD V
VL3 Input mode 3 voltage 100 kΩ ± 5% to AGND 0.27*AVDD 0.33*AVDD 0.4*AVDD V
VL4 Input mode 4 voltage Hi-Z 0.45*AVDD 0.5*AVDD 0.55*AVDD V
VL5 Input mode 5 voltage 100 kΩ ± 5% to AVDD 0.6*AVDD 0.66*AVDD 0.73*AVDD V
VL6 Input mode 6 voltage 22 kΩ ± 5% to AVDD 0.77*AVDD 0.85*AVDD 0.9*AVDD V
VL7 Input mode 7 voltage Tied to AVDD 0.94*AVDD AVDD V
RPU Input pullup resistance To AVDD 80 100 120 kΩ
RPD Input pulldown resistance To AGND 80 100 120 kΩ
OPEN-DRAIN OUTPUTS (FGOUT, nFAULT)
VOL Output logic low voltage IOD = 5 mA 0.4 V
IOH Output logic high current VOD = 5 V –1 1 µA
COD Output capacitance 30 pF
PUSH-PULL OUTPUTS (SDO)
VOL Output logic low voltage IOP = 5 mA 0 0.4 V
VOH Output logic high voltage IOP = 5 mA 2.2 5.5 V
IOL Output logic low leakage current VOP = 0 V –1 1 µA
IOH Output logic high leakage current VOP = 5 V –1 1 µA
COD Output capacitance 30 pF
DRIVER OUTPUTS
RDS(ON) Total MOSFET on resistance (High-side + Low-side) VVM > 6 V, IOUT = 1 A, TA = 25°C 95 120 mΩ
VVM < 6 V, IOUT = 1 A, TA = 25°C 105 130 mΩ
VVM > 6 V, IOUT = 1 A, TJ = 150 °C 140 185 mΩ
VVM < 6 V, IOUT = 1 A, TJ = 150 °C 145 190 mΩ
SR Phase pin slew rate switching low to high (Rising from 20 % to 80 %)
 		 VVM = 24 V, SLEW = 00b or SLEW pin tied to AGND 14 25 45 V/us
VVM = 24 V, SLEW = 01b or SLEW pin to Hi-Z 30 50 80 V/us
VVM = 24 V, SLEW = 10b or SLEW pin to 47 kΩ +/- 5% to AVDD 80 125 185 V/us
VVM = 24 V, SLEW = 11b or SLEW pin tied to AVDD 130 200 280 V/us
SR Phase pin slew rate switching high to low (Falling from 80 % to 20 %
 		 VVM = 24 V, SLEW = 00b or SLEW pin tied to AGND 14 25 45 V/us
VVM = 24 V, SLEW = 01b or SLEW pin to Hi-Z 30 50 80 V/us
VVM = 24 V, SLEW = 10b or SLEW pin to 47 kΩ +/- 5% to AVDD 80 125 185 V/us
VVM = 24 V, SLEW = 11b or SLEW pin tied to AVDD 110 200 280 V/us
ILEAK Leakage current on OUTx VOUTx = VVM, nSLEEP = 1 5 mA
Leakage current on OUTx  VOUTx = 0 V, nSLEEP = 1 1 µA
tDEAD Output dead time (high to low / low to high) VVM = 24 V, SR = 25 V/µs, HS driver ON to LS driver OFF 1800 3400 ns
VVM = 24 V, SR = 50 V/µs, HS driver ON to LS driver OFF 1100 1550 ns
VVM = 24 V, SR = 125 V/µs, HS driver ON to LS driver OFF 650 1000 ns
VVM = 24 V, SR = 200 V/µs, HS driver ON to LS driver OFF 500 750 ns
tPD Propagation delay (high-side / low-side ON/OFF) VVM = 24 V, PWM = 1 to OUTx transisition, SR = 25 V/µs 2000 4550 ns
VVM = 24 V, PWM = 1 to OUTx transisition, SR = 50V/µs 1200 2150 ns
VVM = 24 V, PWM = 1 to OUTx transisition, SR = 125 V/µs 800 1350 ns
VVM = 24 V, PWM = 1 to OUTx transisition, SR = 200 V/µs 650 1050 ns
tMIN_PULSE Minimum output pulse width
SR = 200 V/µs

 600 ns
HALL COMPARATORS
VICM Input Common Mode Voltage (Hall) 0.5 AVDD – 1.2 V
VHYS Voltage hysteresis (SPI Device) HALL_HYS = 0 1.5 5 8 mV
HALL_HYS = 1 35 50 80 mV
Voltage hysteresis (HW Device) 1.5 5 8 mV
ΔVHYS Hall comparator hysteresis difference Between Hall A, Hall B and Hall C comparator –8 8 mV
VH(MIN) Minimum Hall Differential Voltage 40 mV
II Input leakage current HPX = HNX = 0 V –1 1 μA
tHDG Hall deglitch time 0.6 1.15 1.7 μs
tHEDG Hall Enable deglitch time During Power up 1.4 μs
PULSE-BY-PULSE CURRENT LIMIT
VLIM Voltage on VLIM pin for cycle by cycle current limit AVDD/2 AVDD/2–0.4 V
ILIMIT Current limit corresponding to VLIM pin voltage range 0 8 A
ILIM_AC Current limit accuracy –10 10 %
tBLANK Cycle by cycle current limit blank time 5 µs
ADVANCE ANGLE
θADV Advance Angle Setting
(SPI Device)		 ADVANCE_LVL = 000 b 0 1 °
ADVANCE_LVL = 001 b 3 4 5 °
ADVANCE_LVL = 010 b 6 7 8
°
ADVANCE_LVL = 011 b 10 11 12
°
ADVANCE_LVL = 100 b 13.5 15 16.5
°
ADVANCE_LVL = 101 b 18 20 22
°
ADVANCE_LVL = 110 b 22.5 25 27.5
°
ADVANCE_LVL = 111 b 27 30 33
°
θADV Advance Angle Setting
(HW Device)		 Advance pin tied to AGND 0 1
°
Advance pin tied to 22 kΩ ± 5% to AGND 3 4 5
°
Advance pin tied to 100 kΩ ± 5% to AGND 10 11 12
°
Advance pin tied to Hi-Z 13.5 15 16.5
°
Advance pin tied to 100 kΩ ± 5% to AVDD 18 20 22
°
Advance pin tied to 22 kΩ ± 5% to AVDD 22.5 25 27.5
°
Advance pin tied to Tied to AVDD 27 30 33
°
PROTECTION CIRCUITS
VUVLO Supply undervoltage lockout (UVLO) VM rising 4.3 4.4 4.5 V
VM falling 4.1 4.2 4.3 V
VUVLO_HYS Supply undervoltage lockout hysteresis Rising to falling threshold 140 200 350 mV
tUVLO Supply undervoltage deglitch time 3 5 7 µs
VOVP Supply overvoltage protection (OVP)
(SPI Device)		 Supply rising, OVP_EN = 1, OVP_SEL = 0 32.5 34 35 V
Supply falling, OVP_EN = 1, OVP_SEL = 0 31.8 33 34.3 V
Supply rising, OVP_EN = 1, OVP_SEL = 1 20 22 23 V
Supply falling, OVP_EN = 1, OVP_SEL = 1 19 21 22 V
VOVP_HYS Supply overvoltage protection (OVP)
(SPI Device)		 Rising to falling threshold, OVP_SEL = 1 0.9 1 1.1 V
Rising to falling threshold, OVP_SEL = 0 0.7 0.8 0.9 V
tOVP Supply overvoltage deglitch time 2.5 5 7 µs
VCPUV Charge pump undervoltage lockout (above VM) Supply rising 2.3 2.5 2.7 V
Supply falling 2.2 2.4 2.6 V
VCPUV_HYS Charge pump UVLO hysteresis Rising to falling threshold 75 100 140 mV
VAVDD_UV Analog regulator undervoltage lockout Supply rising 2.7 2.85 3 V
Supply falling 2.5 2.65 2.8 V
VAVDD_UV_HYS Analog regulator undervoltage lockout hysteresis Rising to falling threshold 180 200 240 mV
IOCP Overcurrent protection trip point (SPI Device) OCP_LVL = 0b 10 16 20 A
OCP_LVL = 1b 15 24 28 A
Overcurrent protection trip point (HW Device) OCP pin tied to AGND 10 16 21.5 A
OCP pin tied to AVDD 15 24 31 A
tOCP Overcurrent protection deglitch time
(SPI Device)		 OCP_DEG = 00b 0.06 0.3 0.7 µs
OCP_DEG = 01b 0.2 0.6 1.2 µs
OCP_DEG = 10b 0.6 1.25 1.8 µs
OCP_DEG = 11b 1 1.6 2.5 µs
Overcurrent protection deglitch time
(HW Device)		 0.06 0.3 0.6 µs
tRETRY Overcurrent protection retry time
(SPI Device)		 OCP_RETRY = 0 4 5 6 ms
OCP_RETRY = 1 425 500 575 ms
tRETRY Overcurrent protection retry time
(HW Device)		 4 5 6 ms
tMTR_LOCK Motor lock detection time
(SPI Device)		 MOTOR_LOCK_TDET = 00b 270 300 330 ms
MOTOR_LOCK_TDET = 01b 450 500 550 ms
MOTOR_LOCK_TDET = 10b 900 1000 1100 ms
MOTOR_LOCK_TDET = 11b 4500 5000 5500 ms
tMTR_LOCK Motor lock detection time
(HW Device)		 900 1000 1100 ms
tMTR_LOCK_RETRY Motor lock retry time
(SPI Device)		 MOTOR_LOCK_RETRY = 0b 450 500 550 ms
MOTOR_LOCK_RETRY = 1b 4500 5000 5500 ms
tMTR_LOCK_RETRY Motor lock retry time
(HW Device)		 450 500 550 ms
TOTW Thermal warning temperature Die temperature (TJ) 160 170 180 °C
TOTW_HYS Thermal warning hysteresis Die temperature (TJ) 25 30 35 °C
TTSD Thermal shutdown temperature  Die temperature (TJ) 175 185 195 °C
TTSD_HYS Thermal shutdown hysteresis  Die temperature (TJ) 25 30 35 °C
TTSD_FET Thermal shutdown temperature (FET) Die temperature (TJ) 195 205 215 °C
TTSD_FET Thermal shutdown temperature (FET) Die temperature (TJ) 170 180 190 °C
TTSD_FET_HYS Thermal shutdown hysteresis (FET) Die temperature (TJ) 25 30 35 °C
(1) RLBK is resistance of inductor LBK