ZHCSRT4 august   2023 LV5144

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 说明（续）
  7. 6 Pin Configuration and Functions
    1. 6.1 Wettable Flanks
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Range (VIN)
      2. 8.3.2  Output Voltage Setpoint and Accuracy (FB)
      3. 8.3.3  High-Voltage Bias Supply Regulator (VCC)
      4. 8.3.4  Precision Enable (EN/UVLO)
      5. 8.3.5  Power Good Monitor (PGOOD)
      6. 8.3.6  Switching Frequency (RT, SYNCIN)
        1. 8.3.6.1 Frequency Adjust
        2. 8.3.6.2 Clock Synchronization
      7. 8.3.7  Configurable Soft Start (SS/TRK)
        1. 8.3.7.1 Tracking
      8. 8.3.8  Voltage-Mode Control (COMP)
      9. 8.3.9  Gate Drivers (LO, HO)
      10. 8.3.10 Current Sensing and Overcurrent Protection (ILIM)
      11. 8.3.11 OCP Duty Cycle Limiter
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
      4. 8.4.4 Diode Emulation Mode
      5. 8.4.5 Thermal Shutdown
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Design and Implementation
      2. 9.1.2 Power Train Components
        1. 9.1.2.1 Inductor
        2. 9.1.2.2 Output Capacitors
        3. 9.1.2.3 Input Capacitors
        4. 9.1.2.4 Power MOSFETs
      3. 9.1.3 Control Loop Compensation
      4. 9.1.4 EMI Filter Design
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1 – 12-A High-Efficiency Synchronous Buck DC/DC Regulator
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Design 2 – High Density, 12-V, 8-A Rail From 48-V Telecom Power
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Power Stage Layout
        2. 9.4.1.2 Gate Drive Layout
        3. 9.4.1.3 PWM Controller Layout
        4. 9.4.1.4 Thermal Design and Layout
        5. 9.4.1.5 Ground Plane Design
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 第三方产品免责声明
      2. 10.1.2 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
        1. 10.2.1.1 PCB Layout Resources
        2. 10.2.1.2 Thermal Design Resources
    3. 10.3 接收文档更新通知
    4. 10.4 支持资源
    5. 10.5 Trademarks
    6. 10.6 静电放电警告
    7. 10.7 术语表
  12. 11Mechanical, Packaging, and Orderable Information

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6 Pin Configuration and Functions

GUID-19CF4875-3422-4D7C-9E97-95DFF5617446-low.gif
Connect Exposed Pad on bottom to AGND and PGND on the PCB.
Figure 6-1 20-Pin VQFN With Wettable Flanks in RGY Package(Top View)
Table 6-1 Pin Functions
PINI/O(1)DESCRIPTION
NO.NAME
1EN/UVLOIEnable input and undervoltage lockout programming pin. If the EN/UVLO voltage is below 0.4 V, the controller is in shutdown mode with all functions disabled. If the EN/UVLO voltage is greater than 0.4 V and less than 1.2 V, the regulator is in standby mode with the VCC regulator operational, the SS pin grounded, and no switching at the HO and LO outputs. If the EN/UVLO voltage is above 1.2 V, the SS/TRK voltage can ramp and pulse-width modulated gate-drive signals are delivered to the HO and LO pins. A 10-μA current source is enabled when EN/UVLO exceeds 1.2 V and flows through the external UVLO resistor divider to provide hysteresis. Hysteresis can be adjusted by varying the resistance of the external divider.
2RTIOscillator frequency adjust pin. The internal oscillator is programmed with a single resistor between RT and the AGND. TI recommends a maximum oscillator frequency of 1 MHz. An RT pin resistor is required even when using the SYNCIN pin to synchronize to an external clock.
3SS/TRKISoft start and voltage-tracking pin. An external capacitor and an internal 10-μA current source set the ramp rate of the error amplifier reference during start-up. When the SS/TRK pin voltage is less than 0.8 V, the SS/TRK voltage controls the noninverting input of the error amp. When the SS/TRK voltage exceeds 0.8 V, the amplifier is controlled by the internal 0.8-V reference. SS/TRK is discharged to ground during standby and fault conditions. After start-up, the SS/TRK voltage is clamped 115 mV above the FB pin voltage. If FB falls due to a load fault, SS/TRK is discharged to a level 115 mV above FB to provide a controlled recovery when the fault is removed. Voltage tracking can be implemented by connecting a low impedance reference between 0 V and 0.8 V to the SS/TRK pin. The 10-µA SS/TRK charging current flows into the reference and produces a voltage error if the impedance is not low. Connect a minimum capacitance from SS/TRK to AGND of 2.2 nF.
4COMPOLow impedance output of the internal error amplifier. Connect the loop compensation network between the COMP pin and the FB pin.
5FBIFeedback connection to the inverting input of the internal error amplifier. A resistor divider from the output to this pin sets the output voltage level. The regulation threshold at the FB pin is nominally 0.8 V.
6AGNDPAnalog ground. Return for the internal 0.8-V voltage reference and analog circuits.
7SYNCOUTOSynchronization output. Logic output that provides a clock signal that is 180° out-of-phase with the high-side FET gate drive. Connect SYNCOUT of the primary LV5144 to the SYNCIN pin of a second LV5144 to operate two controllers at the same frequency with 180° interleaved high-side FET switch turn-on transitions. Note that the SYNCOUT pin does not provide 180° interleaving when the controller is operating from an external clock that is different from the free-running frequency set by the RT resistor.
8SYNCINIDual function pin to provide an optional clock input and enable diode emulation by the low-side MOSFET. Connecting a clock signal to the SYNCIN pin synchronizes switching to the external clock. Diode emulation by the low-side MOSFET is disabled when the controller is synchronized to an external clock, and negative inductor current can flow in the low-side MOSFET with light loads. A continuous logic low state at the SYNCIN pin enables diode emulation to prevent reverse current flow in the inductor. Diode emulation results in discontinuous mode operation (DCM) at light loads, which improves efficiency. A logic high state at the SYNCIN pin disables diode emulation, producing forced-PWM (FPWM) operation. During soft start when SYNCIN is high or a clock signal is present, the LV5144 operates in diode emulation mode until the output is in regulation, then gradually increases the SW zero-cross threshold, resulting in a gradual transition from DCM to FPWM.
9NC—No electrical connection
10PGOODOPower-good indicator. This pin is an open-drain output. A high state indicates that the voltage at the FB pin is within a specified tolerance window centered at 0.8 V.
11ILIMICurrent limit adjust and current sense comparator input. A current sourced from the ILIM pin through an external resistor programs the threshold voltage for valley current limiting. The opposite end of the threshold adjust resistor can be connected to either the drain of the low-side MOSFET for RDS(on) sensing or to a current sense resistor connected to the source of the low-side FET.
12PGNDPPower ground return pin for the low-side MOSFET gate driver. Connect directly to the source of the low-side MOSFET or the ground side of a shunt resistor.
13LOPLow-side MOSFET gate drive output. Connect to the gate of the low-side synchronous rectifier FET through a short, low inductance path.
14VCCOOutput of the 7.5-V bias regulator. Locally decouple to PGND using a low-ESR/ESL capacitor located as close as possible to the controller. Controller bias can be supplied from an external supply that is greater than the internal VCC regulation voltage. Use caution when applying external bias to ensure that the applied voltage is not greater than the minimum VIN voltage and does not exceed the VCC pin maximum operating rating. See the Recommended Operating Conditions.
15EP—Pin is internally connected to exposed pad of the package. Connect to GND at the exposed pad to improve heat spreading.
16NC—No electrical connection
17BSTOBootstrap supply for the high-side gate driver. Connect to the bootstrap (boot) capacitor. The bootstrap capacitor supplies current to the high-side FET gate and must be placed as close as possible to controller. If an external bootstrap diode is used to reduce the time required to charge the bootstrap capacitor, connect the cathode of the diode to the BST pin and anode to VCC.
18HOPHigh-side MOSFET gate drive output. Connect to the gate of the high-side MOSFET through a short, low inductance path.
19SWPSwitching node of the buck controller. Connect to the bootstrap capacitor, the source terminal of the high-side MOSFET, and the drain terminal of the low-side MOSFET using short, low inductance paths.
20VINPSupply voltage input for the VCC LDO regulator
—EP—Exposed pad of the package. Electrically isolated. Solder to the system ground plane to reduce thermal resistance.
(1) P = Power, G = Ground, I = Input, O = Output