ZHCSJ52A December   2019  – August 2021 LP875701-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Serial Bus Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Descriptions
      1. 7.3.1 Multi-Phase DC/DC Converters
        1. 7.3.1.1 Overview
        2. 7.3.1.2 Multiphase Switcher Configurations
        3. 7.3.1.3 Buck Converter Load-Current Measurement
        4. 7.3.1.4 Spread-Spectrum Mode
      2. 7.3.2 Sync Clock Functionality
      3. 7.3.3 Power-Up
      4. 7.3.4 Regulator Control
        1. 7.3.4.1 Enabling and Disabling Regulators
      5. 7.3.5 Enable and Disable Sequences
      6. 7.3.6 Device Reset Scenarios
      7. 7.3.7 Diagnosis and Protection Features
        1. 7.3.7.1 Power-Good Information (PGOOD pin)
        2. 7.3.7.2 Warnings for Diagnosis (Interrupt)
          1. 7.3.7.2.1 Output Power Limit
          2. 7.3.7.2.2 Thermal Warning
        3. 7.3.7.3 Protection (Regulator Disable)
          1. 7.3.7.3.1 Short-Circuit and Overload Protection
          2. 7.3.7.3.2 Overvoltage Protection
          3. 7.3.7.3.3 Thermal Shutdown
        4. 7.3.7.4 Fault (Power Down)
          1. 7.3.7.4.1 Undervoltage Lockout
      8. 7.3.8 GPIO Signal Operation
      9. 7.3.9 Digital Signal Filtering
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
    5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Interface
        1. 7.5.1.1 Data Validity
        2. 7.5.1.2 Start and Stop Conditions
        3. 7.5.1.3 Transferring Data
        4. 7.5.1.4 I2C-Compatible Chip Address
        5. 7.5.1.5 Auto-Increment Feature
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
        1.       53
        2. 7.6.1.1  DEV_REV
        3. 7.6.1.2  OTP_REV
        4. 7.6.1.3  BUCK0_CTRL1
        5. 7.6.1.4  BUCK0_DELAY
        6. 7.6.1.5  GPIO2_DELAY
        7. 7.6.1.6  GPIO3_DELAY
        8. 7.6.1.7  RESET
        9. 7.6.1.8  CONFIG
        10. 7.6.1.9  INT_TOP1
        11. 7.6.1.10 INT_TOP2
        12. 7.6.1.11 INT_BUCK_0_1
        13. 7.6.1.12 INT_BUCK_2_3
        14. 7.6.1.13 TOP_STAT
        15. 7.6.1.14 BUCK_0_1_STAT
        16. 7.6.1.15 BUCK_2_3_STAT
        17. 7.6.1.16 TOP_MASK1
        18. 7.6.1.17 TOP_MASK2
        19. 7.6.1.18 BUCK_0_1_MASK
        20. 7.6.1.19 BUCK_2_3_MASK
        21. 7.6.1.20 SEL_I_LOAD
        22. 7.6.1.21 I_LOAD_2
        23. 7.6.1.22 I_LOAD_1
        24. 7.6.1.23 PGOOD_CTRL1
        25. 7.6.1.24 PGOOD_CTRL2
        26. 7.6.1.25 PGOOD_FLT
        27. 7.6.1.26 PLL_CTRL
        28. 7.6.1.27 PIN_FUNCTION
        29. 7.6.1.28 GPIO_CONFIG
        30. 7.6.1.29 GPIO_IN
        31. 7.6.1.30 GPIO_OUT
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Inductor Selection
        2. 8.2.1.2 Input Capacitor Selection
        3. 8.2.1.3 Output Capacitor Selection
        4. 8.2.1.4 Snubber Components
        5. 8.2.1.5 Supply Filtering Components
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 接收文档更新通知
    2. 11.2 支持资源
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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7.3.4.1 Enabling and Disabling Regulators

One or more regulators can be enabled when the device is in STANDBY or ACTIVE state. There are two ways for enable and disable the regulators:

  • Using EN_BUCK0 bit in BUCK0_CTRL1 register (EN_PIN_CTRL0 register bit is 0h)
  • Using EN1, EN2, EN3 control pins (EN_BUCK0 bit is 1h AND EN_PIN_CTRL0 register bit is 1 in BUCK0_CTRL1 register)

If the EN1, EN2, EN3 control pins are used for enable and disable then the control pin is selected with BUCK0_EN_PIN_SELECT[1:0] bits (in BUCK0_CTRL1 register). The delay from the control signal rising edge to enabling of the regulator is set by BUCK0_STARTUP_DELAY[3:0] bits and the delay from control signal falling edge to disabling of the regulator is set by BUCK0_SHUTDOWN_DELAY[3:0] bits in BUCK0_DELAY register. The delays are valid only for EN1, EN2, EN3 signal control. The control with EN_BUCK0 bit is immediate without the delays.

The control of the regulator (with 0-ms delays) is shown in Table 7-3.

Note:

The control of the regulator cannot be changed from one ENx pin to a different ENx pin because the control is ENx signal edge sensitive. The control from ENx pin to register bit and back to the original ENx pin can be done during operation.

Table 7-3 Regulator Control
CONTROL METHODEN_BUCK0EN_PIN_CTRL0BUCK0_EN_PIN_SELECT[1:0]EN1 PINEN2 PINEN3 PINBUCKx
OUTPUT VOLTAGE
Enable and disable control with EN_BUCK0 bit0hDon't CareDon't CareDon't CareDon't CareDon't CareDisabled
1h0hDon't CareDon't CareDon't CareDon't Care1.0 Volt
Enable and disable control with EN1 pin1h1h0hLowDon't CareDon't CareDisabled
1h1h0hHighDon't CareDon't Care1.0 Volt
Enable and disable control with EN2 pin1h1h1hDon't CareLowDon't CareDisabled
1h1h1hDon't CareHighDon't Care1.0 Volt
Enable and disable control with EN3 pin1h1h2hDon't CareDon't CareLowDisabled
1h1h2hDon't CareDon't CareHigh1.0 Volt

The regulator is enabled by the ENx pin or by I2C writing as shown in Figure 7-5. The soft-start circuit limits the in-rush current during start-up. When the output voltage rises to 0.35-V level, the output voltage becomes slew-rate controlled . If there is a short circuit at the output and the output voltage does not increase above 0.35-V level in 1 ms, the regulator is disabled, and interrupt is set. When the output voltage reaches the Power-Good threshold level the BUCKx_PG_INT interrupt flag (in INT_BUCK_x register) is set. The Power-Good interrupt flag can be masked using BUCKx_PG_MASK bit (in BUCKx_MASK register).

The ENx input pins have integrated pulldown resistors. The pulldown resistors are enabled by default, and the host can disable those with ENx_PD bits (in CONFIG register).

GUID-2286C291-B637-45B1-8279-69042A34F2BA-low.gif Figure 7-5 Regulator Enable and Disable