SNVS657 Data sheet | 德州仪器 TI.com.cn

SNVS657E September 2010 – September 2014 LP8550

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾⁽²⁾

	MIN	MAX	UNIT
V_IN	–0.3	24	V
V_LDO	–0.3	6
Voltage on logic pins (VSYNC, PWM, EN, SCLK, SDA)	–0.3	6
Voltage on logic pin (FAULT)	–0.3	V_VDDIO + 0.3
Voltage on analog pins (FILTER, V_DDIO, ISET, FSET)	–0.3	6
V (OUT1...OUT6, SW, FB)	–0.3	44
Continuous power dissipation ⁽³⁾	Internally Limited
Junction temperature (T_J-MAX)		125	°C
Maximum lead temperature (soldering)	See ⁽⁴⁾

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.

(3) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T_J = 150°C (typ.) and disengages at T_J = 130°C (typ.).

(4) For detailed soldering specifications and information, please refer to Application Report AN-1112 DSBGA Wafer Level Chip Scale Package (SNVA009).

7.2 Handling Ratings

			MIN	MAX	UNIT
T_stg	Storage temperature range		–65	150	°C
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	-2	2	kV
		Charged device model (CDM), per JEDEC spec. JESD22-C101, all pins⁽²⁾	–200	200	V
		Machine model	–1	1	kV

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾⁽²⁾

		MIN	MAX	UNIT
V_IN (Figure 27)	Input voltage range	5.5	22	V
V_IN + V_LDO (Figure 31)	Input voltage range	4.5	5.5
V_DDIO		1.65	5
V(OUT1...OUT6, SW, FB)		0	40
T_J	Junction temperature	–30	125	°C
T_A⁽³⁾	Ambient temperature	–30	85	°C

(2) All voltages are with respect to the potential at the GND pins.

(3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (T_A-MAX) is dependent on the maximum operating junction temperature (T_J-MAX-OP = 125°C), the maximum power dissipation of the device in the application (P_D-MAX), and the junction-to ambient thermal resistance of the part/package in the application (R_θJA), as given by the following equation: T_A-MAX = T_J-MAX-OP – (R_θJA × P_D-MAX).

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		DSBGA	UNIT
THERMAL METRIC⁽¹⁾		25 PINS	UNIT
R_θJA	Junction-to-ambient thermal resistance ⁽²⁾	40 - 73	°C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design.

7.5 Electrical Characteristics⁽¹⁾⁽²⁾

Limits are for T_A = 25°C (unless otherwise specified); V_IN = 12 V, V_DDIO = 2.8 V, C_VLDO = 1 μF, L1 = 15 μH, C_IN = 10 μF, C_OUT = 10 μF. R_ISET = 16 kΩ, unless otherwise specified. ⁽³⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
I_IN	Standby supply current	Internal LDO disabled EN=L and PWM=L			1 ⁽⁴⁾	μA
	Normal mode supply current	LDO enabled, boost enabled, no current going through LED outputs 5-MHz PLL Clock		3		mA
		10-MHz PLL Clock		3.7
		20-MHz PLL Clock		4.7
		40-MHz PLL Clock		6.7
f_OSC	Internal oscillator frequency accuracy		–4% –7% ⁽⁴⁾		4% 7%⁽⁴⁾
V_LDO	Internal LDO voltage		4.5 ⁽⁴⁾	5	5.5 ⁽⁴⁾	V
I_LDO	Internal LDO external loading				5	mA

(1) All voltages are with respect to the potential at the GND pins.

(2) Minimum (MIN) and Maximum (MAX) limits are specified by design, test, or statistical analysis. Typical numbers represent the most likely norm.

(3) Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.

(4) Limits apply over the full operating ambient temperature range (–30°C ≤ T_A ≤ 85°C).

7.6 Boost Converter Electrical Characteristics

PARAMETER		TEST CONDITIONS	TYP	MAX	UNIT
RDS_ON	Switch ON resistance	I_SW = 0.5 A	0.12		Ω
V_MAX	Boost maximum output voltage		40		V
I_LOAD	Maximum continuous load current	9 V ≤ V_BATT, V_OUT = 35 V	450		mA
		6 V ≤ V_BATT, V_OUT = 35 V	300
		3 V ≤ V_BATT, V_OUT = 25 V	180
V_OUT/V_IN	Conversion ratio	f_SW = 1.25 MHz		10
f_SW	Switching frequency	BOOST_FREQ = 00 BOOST_FREQ = 01 BOOST_FREQ = 10 BOOST_FREQ = 11	156 312 625 1250		kHz
V_OV	Overvoltage protection voltage		V_BOOST + 1.6V		V
t_PULSE	Switch pulse minimum width	no load	50		ns
t_STARTUP	Start-up time	Note ⁽¹⁾	6		ms
I_MAX	SW pin current limit	BOOST_IMAX = 0 BOOST_IMAX = 1	1.4 2.5		A

(1) Start-up time is measured from the moment boost is activated until the V_OUT crosses 90% of its target value.

7.7 LED Driver Electrical Characteristics

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
I_LEAKAGE	Leakage current	Outputs OUT1 to OUT6, V_OUT = 40 V		0.1	1	μA
I_MAX	Maximum source current OUT1 to OUT6	EN_I_RES = 0, CURRENT[7:0] = FFh		30		mA
I_MAX	Maximum source current OUT1 to OUT6	EN_I_RES = 1, CURRENT[7:0] = FFh		50		mA
I_OUT	Output current accuracy⁽¹⁾	Output current set to 23 mA, EN_I_RES = 1	–3% -4%⁽²⁾		3% 4%⁽²⁾
I_MATCH	Matching⁽¹⁾	Output current set to 23 mA, EN_I_RES = 1		0.5%
PWM_RES	PWM output resolution⁽³⁾	f_LED = 5 kHz, f_PLL = 5 MHz		10		bits
		f_LED = 10 kHz, f_PLL = 5 MHz		9
		f_LED = 20 kHz, f_PLL = 5 MHz		8
		f_LED = 5 kHz, f_PLL = 40 MHz		13
		f_LED = 10 kHz, f_PLL = 40 MHz		12
		f_LED = 20 kHz, f_PLL = 40 MHz		11
f_LED	LED switching frequency⁽³⁾	PWM_FREQ[4:0] = 00000b PLL clock 5 MHz		600		Hz
f_LED	LED switching frequency⁽³⁾	PWM_FREQ[4:0] = 11111b PLL clock 5 MHz		19.2k		Hz
V_SAT	Saturation voltage⁽⁴⁾	Output current set to 20 mA		105	220⁽²⁾	mV
V_SAT	Saturation voltage⁽⁴⁾	Output current set to 30 mA		160	290⁽²⁾	mV

(1) Output Current Accuracy is the difference between the actual value of the output current and programmed value of this current. Matching is the maximum difference from the average. For the constant current sinks on the part (OUT1 to OUT6), the following are determined: the maximum output current (MAX), the minimum output current (MIN), and the average output current of all outputs (AVG). Two matching numbers are calculated: (MAX-AVG)/AVG and (AVG-MIN/AVG). The largest number of the two (worst case) is considered the matching figure. The typical specification provided is the most likely norm of the matching figure for all parts. Note that some manufacturers have different definitions in use.

(2) Limits apply over the full operating ambient temperature range (–30°C ≤ T_A ≤ 85°C).

(3) PWM output resolution and frequency depend on the PLL settings. Please see section PWM Frequency Setting for full description.

(4) Saturation voltage is defined as the voltage when the LED current has dropped 10% from the value measured at 1 V.

7.8 PWM Interface Characteristics

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
f_PWM	PWM frequency range		0.1		25	kHz
t_{MIN_ON}	Minimum pulse ON time			1		μs
t_{MIN_OFF}	Minimum pulse OFF time			1		μs
t_STARTUP	Turnon delay from standby to backlight on	PWM input active, EN pin rise from low to high		6		ms
T_STBY	Turn off delay	PWM input low time for turn off, slope disabled		50		ms
PWM_RES	PWM input resolution	f_IN < 9 kHz f_IN < 4.5 kHz f_IN < 2.2 kHz f_IN < 1.1 kHz		10 11 12 13		bits

7.9 Undervoltage Protection

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_UVLO	V_IN UVLO threshold voltage	UVLO[1:0] = 00		Disabled		V
		UVLO[1:0] = 01, falling	2.55	2.70	2.94
		UVLO[1:0] = 01, rising	2.62	2.76	3.00
		UVLO[1:0] = 10, falling	5.11	5.40	5.68
		UVLO[1:0] = 10, rising	5.38	5.70	5.98
		UVLO[1:0] = 11, falling	7.75	8.10	8.45
		UVLO[1:0] = 11, rising	8.36	8.73	9.20

7.10 Logic Interface Characteristics

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
LOGIC INPUT EN
V_IL	Input low level				0.4⁽¹⁾	V
V_IH	Input high level		1.2⁽¹⁾			V
I_I	Input current		-1⁽¹⁾		1⁽¹⁾	μA
LOGIC INPUT VSYNC
V_IL	Input low level				0.4⁽¹⁾	V
V_IH	Input high level		2.2⁽¹⁾			V
I_I	Input current		–1⁽¹⁾		1⁽¹⁾	μA
f_VSYNC	Frequency range		58	60	55000	Hz
LOGIC INPUT PWM
V_IL	Input low level				0.4⁽¹⁾	V
V_IH	Input high level		2.2⁽¹⁾			V
I_I	Input current		–1⁽¹⁾		1⁽¹⁾	μA
LOGIC INPUTS SCL, SDA
V_IL	Input low level				0.2xV_DDIO⁽¹⁾	V
V_IH	Input high level		0.8xV_DDIO⁽¹⁾			V
I_I	Input current		–1⁽¹⁾		1⁽¹⁾	μA
LOGIC OUTPUTS SDA, FAULT
V_OL	Output low level	I_OUT = 3 mA (pull-up current)		0.3	0.5⁽¹⁾	V
I_L	Output leakage current	V_OUT = 2.8 V	–1⁽¹⁾		1⁽¹⁾	μA

(1) Limits apply over the full operating ambient temperature range (–30°C ≤ T_A ≤ 85°C).

7.11 I²C Serial Bus Timing Parameters (SDA, SCLK) ⁽¹⁾

		MIN	MAX	UNIT
f_CLK	Clock frequency		400	kHz
1	Hold time (repeated) START condition	0.6		μs
2	Clock low time	1.3		μs
3	Clock high time	600		ns
4	Setup time for a repeated START condition	600		ns
5	Data hold time	50		ns
6	Data setup time	100		ns
7	Rise time of SDA and SCL	20+0.1C_b	300	ns
8	Fall time of SDA and SCL	15+0.1C_b	300	ns
9	Setup time for STOP condition	600		ns
10	Bus free time between a STOP and a START condition	1.3		μs
C_b	Capacitive load parameter for each bus line Load of 1 pF corresponds to 1 ns.	10	200	ns