ZHCSD11D September   2014  – December 2018 LP5907-Q1

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Output and Input Capacitors
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 LP5907-Q1 Voltage Options
      2. 7.3.2 Enable (EN)
      3. 7.3.3 Low Output Noise
      4. 7.3.4 Output Automatic Discharge
      5. 7.3.5 Remote Output Capacitor Placement
      6. 7.3.6 Thermal Overload Protection (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable (EN)
      2. 7.4.2 Minimum Operating Input Voltage (VIN)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Power Dissipation and Device Operation
        2. 8.2.2.2 External Capacitors
        3. 8.2.2.3 Input Capacitor
        4. 8.2.2.4 Output Capacitor
        5. 8.2.2.5 Capacitor Characteristics
        6. 8.2.2.6 Remote Capacitor Operation
        7. 8.2.2.7 No-Load Stability
        8. 8.2.2.8 Enable Control
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11器件和文档支持
    1. 11.1 接收文档更新通知
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 术语表
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

10.1 Layout Guidelines

The dynamic performance of the LP5907-Q1 is dependant on the layout of the PCB. PCB layout practices that are adequate for typical LDOs may degrade the PSRR, noise, or transient performance of the LP5907-Q1.

Best performance is achieved by placing CIN and COUT on the same side of the PCB as the LP5907-Q1, and as close as is practical to the package. The ground connections for CIN and COUT must be back to the LP5907-Q1 ground pin using as wide and short copper traces as are practical.

Avoid connections using long trace lengths, narrow trace widths, and/or connections through vias. These add parasitic inductances and resistance that results in inferior performance especially during transient conditions