SNVS336F June   2006  – August 2015 LP38856

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable Operation
      2. 7.3.2 Input Voltage
      3. 7.3.3 Bias Voltage
      4. 7.3.4 Undervoltage Lockout
      5. 7.3.5 Supply Sequencing
      6. 7.3.6 Reverse Voltage
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation with 3 V ≤ VBIAS ≤ 5.5 V , VOUT(TARGET) + 0.3 V ≤ VIN ≤ VBIAS
      2. 7.4.2 Operation with VEN Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External Capacitors
          1. 8.2.2.1.1 Output Capacitor
          2. 8.2.2.1.2 Input Capacitor
          3. 8.2.2.1.3 Bias Capacitor
        2. 8.2.2.2 Power Dissipation and Heatsinking
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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9 Power Supply Recommendations

The LP38856 device is designed to operate from an bias voltage supply range between 3 V and 5.5 V, and the input voltage in the range between VOUT + 0.3 V and VBIAS. Input supply must be well regulated. An input capacitor of at least 10 μF is required.