SNVS247E September   2003  – August 2016 LP3875-ADJ

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Shutdown (SD)
      2. 7.3.2 Short-Circuit Protection
      3. 7.3.3 Dropout Voltage
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Active Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Reverse Current Path
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  External Capacitors
        2. 8.2.2.2  CFF (Feed Forward Capacitor)
        3. 8.2.2.3  Selecting a Capacitor
        4. 8.2.2.4  Capacitor Characteristics
          1. 8.2.2.4.1 Ceramic
          2. 8.2.2.4.2 Tantalum
          3. 8.2.2.4.3 Aluminum
        5. 8.2.2.5  Setting The Output Voltage
        6. 8.2.2.6  Turnon Characteristics for Output Voltages Programmed to 2 V or Less
        7. 8.2.2.7  RFI/EMI Susceptibility
        8. 8.2.2.8  Output Noise
        9. 8.2.2.9  Power Dissipation
        10. 8.2.2.10 Estimating Junction Temperature
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
IN pin to GND pin voltage −0.3 7.5 V
Shutdown (SD) pin to GND pin voltage −0.3 7.5 V
OUT pin to GND pin voltage(3),(4) −0.3 6 V
IOUT Short-circuit protected
Power dissipation(5) Internally limited
Storage temperature, Tstg −65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, contact the TI Sales Office/Distributors for availability and specifications.
(3) If used in a dual-supply system where the regulator load is returned to a negative supply, the output must be diode-clamped to ground.
(4) The output PMOS structure contains a diode between the IN and OUT pins. This diode is normally reverse biased. This diode will get forward biased if the voltage at the output terminal is forced to be higher than the voltage at the input terminal. This diode can typically withstand 200 mA of DC current and 1 A of peak current.
(5) At elevated temperatures, device power dissipation must be derated based on package thermal resistance and heat sink values (if a heat sink is used). If power dissipation causes the junction temperature to exceed specified limits, the device goes into thermal shutdown.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN MAX UNIT
VIN supply voltage(1) 2.5 7 V
Shutdown (SD) voltage −0.3 7 V
Maximum operating current (DC) IOUT 1.5 A
Junction temperature –40 125 °C
(1) The minimum operating value for VIN is equal to either [VOUT(NOM) + VDROPOUT] or 2.5 V, whichever is greater.

6.4 Thermal Information

THERMAL METRIC(1) LP3875-ADJ UNIT
NDC (SOT-223) KTT (TO-263)
5 PINS 5 PINS
RθJA(2) Junction-to-ambient thermal resistance, High K 65.2 40.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 47.2 43.4 °C/W
RθJB Junction-to-board thermal resistance 9.9 23.1 °C/W
ψJT Junction-to-top characterization parameter 3.4 11.5 °C/W
ψJB Junction-to-board characterization parameter 9.7 22 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a 1 °C/W
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
(2) Thermal resistance value RθJA is based on the EIA/JEDEC High-K printed circuit board defined by JESD51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.

6.5 Electrical Characteristics

Unless otherwise specified: TJ = 25°C, VIN = VO(NOM) + 1 V, IL = 10 mA, COUT = 10 µF, VSD = 2 V.
PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT
VADJ ADJ pin voltage VOUT + 1 V ≤ VIN ≤ 7 V
10 mA ≤ IL ≤ 1.5 A		 1.198 1.216 1.234 V
VOUT + 1 V ≤ VIN ≤ 7 V
10 mA ≤ IL ≤ 1.5 A
–40°C to 125°C		 1.180 1.216 1.253 V
IADJ ADJ pin input current VOUT + 1 V ≤ VIN ≤ 7 V
10 mA ≤ IL ≤ 1.5 A		 10 nA
VOUT + 1 V ≤ VIN ≤ 7 V
10 mA ≤ IL ≤ 1.5 A
–40°C to 125°C		 100 nA
ΔVOL Output voltage line regulation(3) VOUT + 1 V ≤ VIN ≤ 7 V 0.02%
VOUT + 1 V ≤ VIN ≤ 7 V, –40°C ≤ TJ ≤ 125°C 0.06%
ΔVO/ ΔIOUT Output voltage load regulation(3) 10 mA ≤ IL ≤ 1.5 A 0.06%
10 mA ≤ IL ≤ 1.5 A, –40°C ≤ TJ ≤ 125°C 0.12%
VIN – VOUT Dropout voltage(4) IL = 150 mA 38 50 mV
IL = 150 mA, –40°C ≤ TJ ≤ 125°C 60
IL = 1.5 A 380 450
IL = 1.5 A, –40°C ≤ TJ ≤ 125°C 550
IGND Ground pin current in normal operation mode IL = 150 mA 5 9 mA
IL = 150 mA,–40°C ≤ TJ ≤ 125°C 10
IL = 1.5 A 6 14
IL = 1.5 A, –40°C ≤ TJ ≤ 125°C 15
IGND Ground pin current in shutdown mode VSD ≤ 0.3 V 0.01 10 µA
–40°C ≤ TJ ≤ 85°C 50
IO(PK) Peak output current VOUT ≥ VO(NOM) – 4% 1.8 A
SHORT CIRCUIT PROTECTION
ISC Short-circuit current 3.2 A
SHUTDOWN INPUT
VSDT Shutdown threshold Output = high VIN V
Output = high, –40°C ≤ TJ ≤ 125°C 2
Output = low 0
Output = low, –40°C ≤ TJ ≤ 125°C 0.3
Td(OFF) Turnoff delay IL = 1.5 A 20 µs
Td(ON) Turnon delay IL = 1.5 A 25 µs
ISD SD input current VSD = VIN 1 nA
AC PARAMETERS
PSRR Ripple rejection VIN = VOUT + 1 V, COUT = 10 µF
VOUT = 3.3 V, ƒ = 120 Hz		 73 dB
VIN = VOUT + 0.5 V, COUT = 10 µF
VOUT = 3.3 V, ƒ = 120 Hz		 57
ρn(l/f) Output noise density f = 120 Hz 0.8 µV
en Output noise voltage BW = 10 Hz – 100 kHz, VOUT = 2.5 V 150 µVRMS
BW = 300 Hz – 300 kH, VOUT = 2.5 V 100
(1) Limits are specified by testing, design, or statistical correlation.
(2) Typical numbers are at 25°C and represent the most likely parametric norm.
(3) Output voltage line regulation is defined as the change in output voltage from the nominal value due to change in the input line voltage. Output voltage load regulation is defined as the change in output voltage from the nominal value due to change in load current. The line and load regulation specification contains only the typical number. However, the limits for line and load regulation are included in the output voltage tolerance specification.
(4) Dropout voltage is defined as the minimum input to output differential voltage at which the output drops 2% below the nominal value. Dropout voltage specification applies only to output voltages of 2.5 V and above. For output voltages below 2.5 V, the dropout voltage is nothing but the input to output differential, because the minimum input voltage is 2.5 V.

6.6 Typical Characteristics

Unless otherwise specified: TJ = 25°C, COUT = 10 µF, CIN = 10 µF, SD pin is tied to VIN, VOUT = 2.5 V, VIN = VO(NOM) + 1 V,
IL = 10 mA
LP3875-ADJ 20074660.gif
Figure 1. Dropout Voltage vs Output Load Current
LP3875-ADJ 20074655.gif
Figure 3. Shutdown IQ vs Junction Temperature
LP3875-ADJ 20074659.gif
Figure 5. DC Line Regulation vs Temperature
LP3875-ADJ 20074654.eps
IL = 1.5 A
Figure 2. Ground Current vs Output Voltage
LP3875-ADJ 20074658.gif
Figure 4. DC Load Regulation vs Junction Temperature
LP3875-ADJ 20074661.gif
Figure 6. Noise vs Frequency