ZHCSA23B September   2011  – June 2019 LMR12010

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      典型应用
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Descriptions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Ratings
    3. 6.3 Electrical Characteristics
    4. 6.4 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Boost Function
      2. 7.3.2 Enable Pin / Shutdown Mode
      3. 7.3.3 Soft Start
      4. 7.3.4 Output Overvoltage Protection
      5. 7.3.5 Undervoltage Lockout
      6. 7.3.6 Current Limit
      7. 7.3.7 Thermal Shutdown
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1.      Typical Application
      2. 8.2.1 Detailed Design Procedure
        1. 8.2.1.1 Custom Design With WEBENCH® Tools
        2. 8.2.1.2 Inductor Selection
        3. 8.2.1.3 Input Capacitor
        4. 8.2.1.4 Output Capacitor
        5. 8.2.1.5 Catch Diode
        6. 8.2.1.6 Boost Diode
        7. 8.2.1.7 Boost Capacitor
        8. 8.2.1.8 Output Voltage
        9. 8.2.1.9 Calculating Efficiency, and Junction Temperature
      3. 8.2.2 Application Curves
  9. 9 Layout
    1. 9.1 Layout Considerations
    2. 9.2 Calculating The LMR12010 Junction Temperature
  10. 10器件和文档支持
    1. 10.1 器件支持
      1. 10.1.1 第三方产品免责声明
      2. 10.1.2 开发支持
        1. 10.1.2.1 使用 WEBENCH® 工具创建定制设计
    2. 10.2 接收文档更新通知
    3. 10.3 社区资源
    4. 10.4 商标
    5. 10.5 静电放电警告
    6. 10.6 Glossary
  11. 11机械、封装和可订购信息

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • DDC|6
散热焊盘机械数据 (封装 | 引脚)

9.1 Layout Considerations

When planning layout there are a few things to consider when trying to achieve a clean, regulated output. The most important consideration when completing the layout is the close coupling of the GND connections of the CIN capacitor and the catch diode D1. These ground ends should be close to one another and be connected to the GND plane with at least two through-holes. Place these components as close to the IC as possible. Next in importance is the location of the GND connection of the COUT capacitor, which should be near the GND connections of CIN and D1.

There should be a continuous ground plane on the bottom layer of a two-layer board except under the switching node island.

The FB pin is a high impedance node and care should be taken to make the FB trace short to avoid noise pickup and inaccurate regulation. The feedback resistors should be placed as close as possible to the IC, with the GND of R2 placed as close as possible to the GND of the IC. The VOUT trace to R1 should be routed away from the inductor and any other traces that are switching.

High AC currents flow through the VIN, SW and VOUT traces, so they must be as short and wide as possible. However, making the traces wide increases radiated noise, so the designer must make this trade-off. Radiated noise can be decreased by choosing a shielded inductor.

The remaining components should also be placed as close as possible to the IC. Refer to the LMR12010 demo board as an example of a good layout.