ZHCSID6A December 2018 – December 2018 LMK05318
PRODUCTION DATA.
After device POR configuration and initialization, APLL1 will automatically lock to the XO clock once it is detected by its input monitor. Then, APLL2 will acquire lock to either VCO1 or XO frequency as selected. The output clock frequency accuracy and stability in free-run mode are equal to that of the XO input. The reference inputs remain invalid (unqualified) during free-run mode.