ZHCSID6A December 2018 – December 2018 LMK05318
PRODUCTION DATA.
Each clock output can be individually configured as a differential driver (AC-LVDS/CML/LVPECL), HCSL driver, or 1.8-V LVCMOS drivers (two per pair). Otherwise, it can be disabled if not used to save power.
Each output channel has its own internal LDO regulator to provide excellent PSNR and minimize jitter and spurs induced by supply noise. The OUT[0:1] channel (mux, divider, and drivers) are powered through a single output supply pin (VDDO_01), and similarly for the OUT[2:3] channel (VDDO_23). Each OUT[4:7] channel have their own output supply pin (VDDO[4:7]). Each output supply can be separately powered by 1.8 V, 2.5 V, or 3.3 V for a differential or HCSL output, or 1.8 V for an LVCMOS output.
For differential and HCSL driver modes, the output clock specifications (such as output swing, phase noise, and jitter) are not sensitive to the VDDO_x voltage because of the channel's internal LDO regulator. When an output channel is left unpowered, the channel's output(s) will not generate any clocks.
OUTx_FMT | OUTPUT FORMAT(1) |
---|---|
00h | Disabled (powered-down) |
10h | AC-LVDS |
14h | AC-CML |
18h | AC-LVPECL |
2Ch | HCSL (External 50-Ω to GND) |
2Dh | HCSL (Internal 50-Ω to GND) |
30h | LVCMOS (HiZ / HiZ) |
32h | LVCMOS (HiZ / –) |
33h | LVCMOS (HiZ / +) |
35h | LVCMOS (Low / Low) |
38h | LVCMOS (– / HiZ) |
3Ah | LVCMOS (– / –) |
3Bh | LVCMOS (– / +) |
3Ch | LVCMOS (+ / HiZ) |
3Eh | LVCMOS (+ / –) |
3Fh | LVCMOS (+ / +) |