9.1 Overview

The LMK05318 has two reference inputs, one digital PLL (DPLL), two analog PLLs (APLLs) with integrated VCOs, and eight output clocks. with RMS phase jitter of 50-fs typical from APLL1 and 125-fs typical from APLL2. APLL1 uses an ultra-high performance BAW VCO (VCO1) with a very high quality factor, and thus has no dependency on the phase noise or frequency of the external oscillator (XO) input clock. This minimizes the overall solution cost and allows the use of an off-the-shelf XO, TCXO, or OCXO selected to meet the free-run and holdover frequency stability requirements of the application. APLL1 is cascaded with the DPLL, allowing the APLL1 domain to be locked to the DPLL reference input for synchronous clock generation. APLL2 can be used to generate unrelated clock frequencies either locked to the APLL1 domain or the free-running XO input.

The DPLL reference input mux supports automatic input selection or manual input selection through software or pin control. The device provides hitless switching with proprietary phase cancellation for superior phase transient performance (±50 ps typical). The reference clock input monitoring block monitors the clock inputs and will perform a hitless switchover or holdover when a loss of reference (LOR) is detected. A LOR condition can be detected upon any violation of the threshold limits set for the input monitors, which include amplitude, frequency, missing pulse, runt pulse, and 1-PPS (pulse-per-second) detectors. The threshold limits for each input detector can be set and enabled per clock input. The tuning word history monitor feature allows the initial output frequency accuracy upon entry into holdover to be determined by the historical average frequency when locked, minimizing the frequency and phase disturbance during a LOR condition.

The device has eight outputs with programmable drivers, allowing up to eight differential clocks, or a combination of differential clocks and up to four 1.8-V LVCMOS pairs (two outputs per pair). The output clocks can be selected from either APLL/VCO domain through the output muxes. The output dividers have a SYNC feature to allow multiple outputs to be phase-aligned. A 1-PPS output can be supported on Output 7 (OUT7). If needed, the user can enable the zero-delay mode (ZDM) synchronization to achieve deterministic phase alignment between an APLL1 clock on OUT7 and the selected reference input.

To support IEEE 1588 PTP slave clock or other clock steering applications, the DPLL also supports DCO mode with less than 0.001-ppb (part per billion) frequency resolution for precise frequency and phase adjustment through external software or pin control.

The device is fully programmable through I²C or SPI and supports custom start-up frequency configuration with the internal EEPROM, which is factory pre-programmed and in-system programmable if needed. Internal LDO regulators provide excellent PSNR to reduce the cost and complexity of the power delivery network. The clock input and PLL monitoring status can be observed through the status pins and interrupt registers for full diagnostic capability.