10.1 Layout Guidelines
The following guidelines should be followed when designing the layout:
- Set trace impedances to 75-Ω ± 5% single ended, 100-Ω ± 5% differential.
- Maintain the same signal reference plane for 75-Ω single-end trace, and reference plane for 100-Ω differential traces.
- Use the smallest size surface mount components.
- Use solid planes. Provide GND or VDD relief under the component pads to minimize parasitic capacitance.
- Select trace widths that minimize the impedance mismatch along the signal path.
- Select a board stack-up that supports 75-Ω or 50-Ω single-end trace, 100-Ω coupled differential traces.
- Use surface mount ceramic capacitors.
- Place BNC component within 1 inches of the LMH1218 device.
- Maintain symmetry on the complimentary signals.
- Route 100-Ω traces uniformly (keep trace widths and trace spacing uniform along the trace).
- Avoid sharp bends; use 45-degree or radial bends.
- Walk along the signal path, identify geometry changes and estimate their impedance changes.
- Maintain 75-Ω impedance with a well-designed connectors’ footprint.
- Consult a 3-D simulation tool to guide layout decisions.
- Use the shortest path for VDD and Ground hook-ups; connect pin to planes with vias to minimize or eliminate trace.
- When a high speed trace changes layer, provide at least 2 return vias to improve current return path.