ZHCSE54 September   2015 LMH0318

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 说明（续）
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Recommended SMBus Interface AC Timing Specifications
    7. 7.7 Serial Parallel Interface (SPI) Bus Interface AC Timing Specifications
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Loss of Signal Detector
      2. 8.3.2 Continuous Time Linear Equalizer (CTLE)
      3. 8.3.3 2:1 Multiplexer
      4. 8.3.4 Clock and Data Recovery
      5. 8.3.5 Eye Opening Monitor (EOM)
      6. 8.3.6 Fast EOM
        1. 8.3.6.1 SMBus Fast EOM Operation
        2. 8.3.6.2 SPI Fast EOM Operation
      7. 8.3.7 LMH0318 Device Configuration
        1. 8.3.7.1 MODE_SEL
        2. 8.3.7.2 ENABLE
        3. 8.3.7.3 LOS_INT_N
        4. 8.3.7.4 LOCK
        5. 8.3.7.5 SMBus MODE
        6. 8.3.7.6 SMBus READ/WRITE Transaction
        7. 8.3.7.7 SPI Mode
          1. 8.3.7.7.1 SPI READ/WRITE Transaction
          2. 8.3.7.7.2 SPI Write Transaction Format
          3. 8.3.7.7.3 SPI Read Transaction Format
        8. 8.3.7.8 SPI Daisy Chain
          1. 8.3.7.8.1 SPI Daisy Chain Write Example
          2. 8.3.7.8.2 SPI Daisy Chain Write Read Example
            1. 8.3.7.8.2.1 SPI Daisy Chain Length of Daisy Chain Illustration
      8. 8.3.8 Power-On Reset
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 Register Maps
      2. 8.5.2 Global Registers
      3. 8.5.3 Receiver Registers
      4. 8.5.4 CDR Registers
      5. 8.5.5 Transmitter Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 General Guidance for All Applications
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don'ts
    4. 9.4 Initialization Set Up
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Solder Profile
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 开发支持
    2. 12.2 文档支持
      1. 12.2.1 相关文档　
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Specifications

7.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply Voltage (VDD to GND) -0.5 2.75 V
3.3 V Open drain I/O input/output voltage (SDA, SCL, LOS_INT_N) -0.5 4.0 V
2.5V LVCMOS Input/Output Voltage -0.5 2.75 V
High Speed input Voltage -0.5 2.75 V
High Speed Input Current -30 30 mA
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Absolute Maximum Numbers are ensured for a junction temperature range of -40°C to +125°C. Models are validated to Maximum Operating Voltages only.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4500 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±4500 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±1500 V may actually have higher performance.

7.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)
MIN TYP MAX UNIT
Supply voltage(1) 2.375 2.5 2.625 V
3.3 V Open drain I/O input/output voltage(1) 3 3.3 3.6 V
Supply noise, 50 Hz to 10 MHz, sinusoidal 40 mVpp
Ambient Temperature -40 25 85 ºC
Source transmit differential launch amplitude 300 500 1000 mVP-P
SMBus clock frequency (SCL) in SMBus slave mode 100 400 kHz
SMBUS SDA and SCL Voltage Level 3.6 V
SPI Clock Frequency 10 20 MHz
(1) DC plus AC power should not exceed these limits.

7.4 Thermal Information

THERMAL METRIC(1)(2) RTWA0024A UNIT
24 PINS
RθJA Junction-to-ambient thermal resistance 34 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 31.4
RθJB Junction-to-board thermal resistance 11.8
ψJT Junction-to-top characterization parameter 0.3
ψJB Junction-to-board characterization parameter 11.8
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.7
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) No heat sink is assumed for these estimations. Depending on the application, a heat sink, faster air flow, and/or reduced ambient temperature ( < 85ºC) may be required in order to maintain the maximum junction temperature specified in Electrical Characteristics.

7.5 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER
PD Power dissipation Locked 75 Ω OUT0 only (800 mVpp), EOM powered down 300 mW
Locked OUT1 only (600 mVpp, diff), EOM powered down 195 mW
Transient power during CDR lock acquisition, 75 Ω OUT0 and OUT1 powered up, EOM powered down 400 500 mW
PD_RAW Power dissipation in force RAW mode (CDR bypass) EQ bypass, OUT0 720mVpp, OUT1 600mVpp
IN0 to OUT0 and OUT1 or IN1 to OUT0 and OUT1		 195 mW
IN0 to OUT0, OUT1 powered down 160 mW
IN1 to OUT1, OUT0 powered down 80 mW
4-LEVEL INPUT and 2.5 V LVCMOS DC SPECIFICATIONS
VIH High level input voltage 4-level input (MODE_SEL, ADDR0/1, ENABLE pins) 0.95*VDD V
VIF Float level input voltage 4-level input (MODE_SEL, ADDR0/1, ENABLE pins) 0.67*VDD V
VI20K 20K to GND input voltage 4-level input (MODE_SEL, ADDR0/1, ENABLE pins) 0.33*VDD V
VIL Low level input voltage 4-level input (MODE_SEL, ADDR0/1, ENABLE pins) 0.1 V
VOH High level output voltage IOH = -3 mA 2 V
VOL Low level output voltage IOL = 3 mA 0.4 V
IIH Input high leakage current
 Vinput = VDD
SPI Mode: LVCMOS (SPI_SCK, SPI_SS_N) pins		 15 µA
SMBus Mode: LVCMOS (SMB_SDA, SMB_SCL) pins 15 µA
SMBus Mode: 4-Levels (ADDR0, ADDR1) pins 20 44 80 µA
4-Levels (MODE_SEL, ENABLE) pins 20 44 80 µA
IIL Input low leakage current
 Vinput = GND
SPI Mode: LVCMOS (SPI_MOSI, SPI_SCK) pins		 -15 µA
Vinput = GND
SPI Mode: LVCMOS (SPI_SS_N) pins		 -37 µA
SMBus Mode: LVCMOS (SMB_SDA, SMB_SCL pins -15 µA
SMBus Mode: 4-Levels (ADDR0, ADDR1) pins -160 -93 -40 µA
4-Levels (MODE_SEL, ENABLE) pins -160 -93 -40 µA
3.3-V TOLERANT LVCMOS / LVTTL DC SPECIFICATIONS (SDA, SCL, LOS_INT_N)
VIH25 High level input voltage 2.5 V Supply Voltage 1.75 3.6 V
VIL Low level input voltage GND 0.8 V
VOL Low level output voltage IOL = 1.25 mA 0.4 V
IIH Input high current VIN = 2.5 V, VDD = 2.5 V 20 40 μA
IIL Input low current VIN = GND, VDD = 2.5 V -10 10 μA
SIGNAL DETECT
SDH Signal detect (default)
Assert threshold level(2)(3)		 2.97 Gbps, EQ Pathological Pattern 22 mVP-P
2.97 Gbps, PLL Pathological Pattern 22 mVP-P
2.97 Gbps, PRBS10 Pattern 22 mVP-P
SDL Signal detect (default)
De-assert threshold level(2)		 2.97 Gbps EQ Pathological Pattern 16 mVP-P
2.97 Gbps, PLL Pathological Pattern 16 mVP-P
2.97 Gbps, PRBS10 Pattern 9 mVP-P
HIGH SPEED RECEIVE RX INPUTS (IN_n+, IN_n-)
R_RD DC Input differential resistance 75 100 125 Ω
RLRX-SDD Input differential return loss(1)(5) Measured with the device powered up.
SDD11 10 MHz to 2 GHz		 -14  dB
SDD11 2 GHz to 3 GHz -6.5  dB
RLRX-SCD Differential to common mode Input conversion(1)(5) Measure with the device powered up.SCD11, 10 MHz to 3 GHz  -20 dB
HIGH SPEED OUTPUTS (OUT_n+, OUT_n-)
VVOD_OUT1 Output differential voltage(1)(5) Default setting, 8T clock pattern 400 600 700 mVP-P
VVOD_OUT1_DE De-emphasis Level VOD = 600mV, maximum De-Emphasis with 16T clock pattern -9 dB
VVOD_OUT1_CLK Clock output differential voltage 2.97 GHz,1.485 GHz, and 270 MHz 560 mVP-P
VVOD_OUT0 Output single ended voltage at OUT0+ with OUT0- terminated(9)(1) Default setting 720 800 880 mVP-P
RDIFF_OUT1 DC output differential resistance 100 Ω
RDIFF_OUT0 DC output single ended resistance 75 Ω
TR_F_OUT1 Output rise/fall time Full Slew Rate, 20% to 80% using 8T Pattern 45 ps
TR_F_OUT0 Output rise/fall time, PRBS15 (1)(5) 2.97 Gbps 35 45 ps
1.485 Gbps 35 45 ps
270 Mbps 400 900 1500 ps
TR_F_OUT0_delta Output rise/fall time mismatch(1)(5) 2.97 Gbps 3 18 ps
1.485 Gbps 3 18 ps
270 Mbps 72 500 ps
VOVR_UDR_SHOOT Output overshoot, undershoot(1) (5) 3G/HD/SD Measured with 8T pattern 2.4% <10%
VDC_OFFSET DC offset 3G/HD/SD ±0.2 V
VDC_WANDER DC wander 3G/HD/SD EQ Pathological 20 mV
RLOUT0_S22 OUT0 single ended 75-Ω return loss(1)(5)(7) S22 5 MHz to 1.485 GHz < -15 dB
S22 1.485 GHz to 3 GHz < -10 dB
RLOUT1_SDD22 OUT1 differential 100-Ω return loss(5)(6) SDD22 10 MHz - 2 GHz -20  dB
SDD22 2 GHz - 3 GHz  -17 dB
RLOUT1_SCC22 OUT1 common mode 50-Ω return loss(5)(6) SCC22 10 MHz - 3 GHz -11 dB
VVCM_OUT1_NOISE AC common mode voltage noise(5) VOD = 0.6 Vpp, DE = 0dB, PRBS31, 2.97 Gbps 8 mVRMS
TRCK_LATENCY Latency reclocked Reclocked Data 1.5 UI +195 ps
TRAW_LATENCY Latency CDR bypass Raw Data 230 ps
TRANSMIT OUTPUT JITTER SPECIFICATIONS
AJ_OUT0 Alignment jitter(5) OUT0, PRBS15, 2.97 Gbps 0.045 UI
TJ_OUT1 Total jitter (1E-12)(5) OUT1, PRBS15 2.97 Gbps 0.06 UI
RJ_OUT1 Random jitter (rms) OUT1, PRBS15, 2.97 Gbps 0.91 psRMS
DJ_OUT1 Deterministic jitter OUT1, PRBS15, 2.97 Gbps 6.8 psP-P
CLOCK DATA RECOVERY
DDATA_RATE SMPTE 424(8) 2.970
2.967		 Gbps
SMPTE 292(8) 1.485
1.4835		 Gbps
SMPTE 259M(8) 270 Mbps
PPLL_BW PLL bandwidth at -3 dB Measured with 0.2UI SJ at 2.97 Gbps 5 MHz
Measured with 0.2UI SJ at 1.485 Gbps 3 MHz
Measured with 0.2UI SJ at 270 Mbps 1 MHz
JTOL Total input jitter tolerance TJ = DJ + RJ + SJ,
DJ+RJ = 0.15 UI
SJ/PJ, low to high upward sweep (10 kHz to 10 MHz)		 0.65 UI
TLOCK Lock time(1)(4) From signal detected to the lock asserted, HEO/VEO lock monitor disable, same setting for 2.97G, 1.485G and 270 MHz data rates <5 ms
TTEMP_LOCK CDR lock with temperature ramp Temperature Lock Range, 5ºC per minute ramp up and down, -40ºC to 85ºC operating range 125 °C
(1) These limits are ensured by bench characterization and are not production tested.
(2) Data with extraordinarily long periods of high-frequency 1010 data, and for long, lossy channels, the signal amplitude at the input to the device may be severely attenuated by the channel and may fall below the signal detect assert and/or de-assert thresholds.
(3) The voltage noise on the receiver inputs which has an amplitude larger than the signal detect assert threshold may trigger a signal detect assert condition
(4) The total CDR lock time depends on number of rate settings enabled and application data rate
(5) Dependent on board layout. Characterization data was measured with LMH1218EVM evaluation board
(6) Measure with the device powered up and outputs a clock signal.
(7) Output return loss is dependent on board design, this is measured with the LMH1218EVM evaluation board
(8) Data rate tolerance is within ±1000 ppm
(9) ATE Production tested using DC method. Apply differential DC signal at the input and measure OUT0P amplitude. OUT0N terminated in 75 Ohm.

7.6 Recommended SMBus Interface AC Timing Specifications(1)(2)(3)

Over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fSMB Bus operating frequency MODE_SEL = 0 10 100 400 kHz
tBUF Bus free time between stop and start condition 1.3 μs
tHD:STA Hold time after (repeated) start condition
After this period, the first clock is generated		 0.6 μs
tSU:STA Repeated start condition setup time 0.6 μs
tSU:STO Stop condition setup time 0.6 μs
tHD:DAT Data hold time 0 ns
tSU:DAT Data setup time 100 ns
tLOW Clock low period 1.3 μs
tHIGH Clock high period 0.6 50 μs
tF SDA fall time read operation 300 ns
tR SDA rise time read operation 300 ns
(1) SMBus operation is available 20ms after power up
(2) These specifications support SMBus 2.0 specifications
(3) These Parameters are not production tested

7.7 Serial Parallel Interface (SPI) Bus Interface AC Timing Specifications(1)(2)(3)

Over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f SCK SCK frequency MODE_SEL = 1 10 20 MHz
TSCK SCK period 50 ns
tPH SCK pulse width high 0.40*TSCK ns
tPL SCK pulse width low 0.40*TSCK ns
tSU MOSI setup time 4 ns
tH MOSI hold time 4 ns
tSSSu SS_N setup time 14 18 ns
tSSH SS_N hold time 4 ns
tSSOF SS_N off time 1 μs
tODZ MISO driven to TRI-STATE time 20 ns
tOZD MISO TRI-STATE-to-Driven time 10 ns
tOD MISO output delay time 15 ns
(1) Typical values are parametric norms at VDD = 2.5 V, TA = 25ºC, and recommended operating conditions at the time of product characterization. Typical values are not production tested.
(2) These specifications support SPI 1.0 specifications.
(3) These Parameters are not production tested

7.8 Typical Characteristics

Typical device characteristics at TA = +25°C and VDD = 2.5 V, unless otherwise noted.
LMH0318 LMH0318_3G_OUT0.gif
Figure 1. 75 Ω OUT0 PRBS10 at 2.97 Gbps
LMH0318 LMH0318_HD_OUT0.gif
Figure 2. 75 Ω OUT0 PRBS10 at 1.485 Gbps