Table 46. Design Parameters

10.2.1.2.1 Select R_SNS and CL Setting

LM5066 can be used with a VCL of 26 or 50 mV. Using the 26-mV threshold results in a lower R_SNS and lower I²R losses, but using the 50-mV threshold would result in better current and power monitoring accuracy along with a lower minimum power limit . The 26-mV option is selected for this design by connecting the CL pin directly to V_DD. TI recommends to target a current limit that is at least 10% above the maximum load current to account for the tolerance of the LM5066 current limit. Targeting a current limit of 11 A, the sense resistor can be computed as follows:

Equation 5.

Typically, sense resistors are only available in discrete values. If a precise current limit is desired, a sense resistor along with a resistor divider can be used as shown in Figure 29.

Figure 29. SENSE Resistor Divider

The next larger available sense resistor should be chosen (3 mΩ in this case). The ratio of R₁ and R₂ can be computed as follows:

Equation 6.

Note that the SENSE pin pulls 25 μA of current, which creates an offset across R₂. TI recommends to keep R₂ below 10 Ω to reduce the offset that this introduces. In addition, the 1% resistors add to the current monitoring error. Finally, if the resistor divider approach is used, the user should compute the effective sense resistance (R_SNS,EFF) using Equation 7 and use that in all equations instead of R_SNS.

Equation 7.

Note that for many applications, a precise current limit may not be required. In that case, it is simpler to pick the next smaller available sense resistor. For this application, a 2-mΩ resistor can be used for a 13-A current limit.

10.2.1.2.2 Selecting the Hotswap FETs

It is critical to select the correct MOSFET for a hotswap design. The device must meet the following requirements:

• The V_DS rating should be sufficient to handle the maximum system voltage along with any ringing caused by transients. For most 48-V systems, a 100-V FET is a good choice.
• The SOA of the FET should be sufficient to handle all usage cases: start-up, hot-short, and start into short.
• R_DSON should be sufficiently low to maintain the junction and case temperature below the maximum rating of the FET. In fact, TI recommends to keep the steady-state FET temperature below 125°C to allow margin to handle transients.
• Maximum continuous current rating should be above the maximum load current and the pulsed-drain current must be greater than the current threshold of the circuit breaker. Most MOSFETs that pass the first three requirements also pass these two.
• A V_GS rating of ±20 V is required because the LM5066 can pull up the gate as high as 16 V above source.

For this design, the PSMN4R8-100BSE was selected for its low R_DSON and superior SOA. After selecting the MOSFET, the maximum steady-state case temperature can be computed as follows:

Equation 8.

Note that the R_DSON is a strong function of junction temperature, which for most D2PACK MOSFETs is very close to the case temperature. A few iterations of the previous equations may be necessary to converge on the final R_DSON and T_C,MAX value. According to the PSMN4R8-100BSE data sheet, it's R_DSON doubles at 110°C. Equation 9 uses this R_DSON value to compute the T_C,MAX. Note that the computed T_C,MAX is close to the junction temperature assumed for R_DSON. Thus, no further iterations are necessary.

Equation 9.

10.2.1.2.3 Select Power Limit

In general, a lower power limit setting is preferred to reduce the stress on the MOSFET. However, when the LM5066 is set to a very-low power limit setting, it has to regulate the FET current and hence the voltage across the sense resistor (V_SNS) to a very-low value. V_SNS can be computed as shown in Equation 10.

Equation 10.

To avoid significant degradation of the power limiting, TI does not recommend a V_SNS of less than 4 mV. Based on this requirement, the minimum allowed power limit can be computed as follows:

Equation 11.

In most applications, the power limit can be set to P_LIM,MIN using Equation 12. Note that the P_LIM of the LM5066 will have some variations vs V_DS of the MOSFET due to a 1.5-mV systematic offset. Equation 12 sets R_PWR to make the actual power limit equal the programmed power limit at V_IN = V_IN,MAX and V_OUT = 0 V.

Equation 12.

The closest available resistor should be selected. In this case, a 21-kΩ resistor was chosen.

10.2.1.2.4 Set Fault Timer

The fault timer runs when the hotswap is in power limit or current limit, which is the case during start-up. Thus, the timer has to be sized large enough to prevent a time-out during start-up. If the part starts directly into current limit (I_LIM × V_DS < P_LIM), the maximum start time can be computed with Equation 13.

Equation 13.

For most designs (including this example), I_LIM × V_DS > P_LIM, so the hotswap starts in power limit and transitions into current limit. In that case, the maximum start time can be computed as in Equation 14.

Equation 14.

Note that the above start-time is based on typical current limit and power limit values. To ensure that the timer never times out during start-up, TI recommends to set the fault time (t_flt) to be 2 × t_start,max or 6.76 ms. This accounts for the variation in power limit, timer current, and timer capacitance. Thus, C_TIMER can be computed as follows:

Equation 15.

The next largest standards capacitor value for C_TIMER is chosen as 150 nF. After C_TIMER is chosen, the actual programmed fault time can be computed as follows:

Equation 16.

10.2.1.2.5 Check MOSFET SOA

When the power limit and fault timer are chosen, it is critical to check that the FET stays within its SOA during all test conditions. During a hot-short the circuit breaker trips and the LM5066 restarts into power limit until the timer runs out. In the worst case, the MOSFET’s V_DS equals V_IN,MAX, I_DS equals P_LIM / V_IN,MAX and the stress event lasts for t_flt. For this design example, the MOSFET has 60 V, 2 A across it for 7.8 ms.

Based on the SOA of the PSMN4R8-100BSE, it can handle 60 V, 30 A for 1 ms and it can handle 60 V, 6 A for 10 ms. For 7.8 ms, the SOA can be extrapolated by approximating SOA versus time as a power function as shown below:

Equation 17.

Note that the SOA of a MOSFET is specified at a case temperature of 25°C, while the case temperature can be much hotter during a hot-short. The SOA should be de-rated based on T_C,MAX using Equation 18:

Equation 18.

Based on this calculation, the MOSFET can handle 2.85 A, 60 V for 7.8 ms at elevated case temperature, but is only required to handle 2 A during a hot-short. Thus, there is good margin and the design is robust. In general, TI recommends that the MOSFET can handle 1.3× more than what is required during a hot-short. This provides margin to account for the variance of the power limit and fault time.

10.2.1.2.6 Set UVLO and OVLO Thresholds

By programming the UVLO and OVLO thresholds, the LM5066 enables the series-pass device (Q₁) when the input supply voltage (V_IN) is within the desired operational range. If V_IN is below the UVLO threshold or above the OVLO threshold, Q₁ is switched off, denying power to the load. Hysteresis is provided for each threshold.

10.2.1.2.6.1 Option A

The configuration shown in Figure 30 requires three resistors (R1 to R3) to set the thresholds.

Figure 30. UVLO And OVLO Thresholds Set By R1-R3

The procedure to calculate the resistor values is as follows:

• Choose the upper UVLO threshold (V_UVH) and the lower UVLO threshold (V_UVL).
• Choose the upper OVLO threshold (V_OVH).
• The lower OVLO threshold (V_OVL) cannot be chosen in advance in this case, but is determined after the values for R1 to R3 are determined. If V_OVL must be accurately defined in addition to the other three thresholds, see Option B. The resistors are calculated as follows:

Equation 19.

Equation 20.

Equation 21.

The lower OVLO threshold is calculated from:

Equation 22.

When the R1 to R3 resistor values are known, the threshold voltages and hysteresis are calculated from the following:

Equation 23.

Equation 24.

Equation 25.

Equation 26.

Equation 27.

Equation 28.

10.2.1.2.6.2 Option B

If all four thresholds must be accurately defined, the configuration in Figure 31 can be used.

Figure 31. Programming the Four Thresholds

The four resistor values are calculated as follows:

• Choose the upper and lower UVLO thresholds (V_UVH) and (V_UVL).
Equation 29.
Equation 30.
• Choose the upper and lower OVLO threshold (V_OVH) and (V_OVL).
Equation 31.
Equation 32.
• When the R1 to R4 resistor values are known, the threshold voltages and hysteresis are calculated from the following:

Equation 33.

Equation 34.

Equation 35.

Equation 36.

Equation 37.

10.2.1.2.6.3 Option C

The minimum UVLO level is obtained by connecting the UVLO/EN pin to VIN as shown in Figure 32. Q1 is switched on when the VIN voltage reaches the POR_EN threshold (≊8.6 V). The OVLO thresholds are set using R3, R4. Their values are calculated using the procedure in Option B.

Figure 32. UVLO = POR_EN

10.2.1.2.6.4 Option D

The OVLO function can be disabled by grounding the OVLO pin. The UVLO thresholds are set as described in Option B or Option C.

For this design example, option B was used and the following options were targeted: V_UVH = 38 V, V_UVL = 35 V, V_OVH = 65 V, and V_OVL = 63 V. The V_UVH and V_OVL were chosen to be 5% below or above the input voltage range of 40 to 60 V to allow for some tolerance in the thresholds of the part. R1, R2, R3, and R4 are computed using the following equations:

Equation 38.

Nearest available 1% resistors should be chosen. Set R1 = 150 kΩ, R2 = 11.5 kΩ, R3 = 95.3 kΩ, and R4 = 3.74 kΩ.

10.2.1.2.7 Power Good Pin

The Power Good indicator pin (PGD) is connected to the drain of an internal N-channel MOSFET capable of sustaining 80 V in the off-state and transients up to 100 V. An external pullup resistor is required at PGD to an appropriate voltage to indicate the status to downstream circuitry. The off-state voltage at the PGD pin can be higher or lower than the voltages at VIN and OUT. PGD is switched high when the voltage at the FB pin exceeds the PGD threshold voltage. Typically, the output voltage threshold is set with a resistor divider from output to feedback, although the monitored voltage need not be the output voltage. Any other voltage can be monitored as long as the voltage at the FB pin does not exceed its maximum rating. Referring to the Functional Block Diagram, when the voltage at the FB pin is below its threshold, the 20-µA current source at FB is disabled. As the output voltage increases, taking FB above its threshold, the current source is enabled, sourcing current out of the pin, raising the voltage at FB to provide threshold hysteresis. The PGD output is forced low when either the UVLO/EN pin is below its threshold or the OVLO pin is above its threshold. The status of the PGD pin can be read through the PMBus interface in either the STATUS_WORD (79h) or DIAGNOSTIC_WORD (E1h) registers.

When the voltage at the FB pin increases above its threshold, the internal pulldown acting on the PGD pin is disabled allowing PGD to rise to V_PGD through the pullup resistor, R_PG, as shown in Figure 34. The pullup voltage (V_PGD) can be as high as 80 V, and can be higher or lower than the voltages at VIN and OUT. VDD is a convenient choice for V_PGD as it allows interface to low voltage logic and avoids glitching on PGD during power-up. If a delay is required at PGD, suggested circuits are shown in Figure 35. In Figure 35(A), capacitor C_PG adds delay to the rising edge, but not to the falling edge. In Figure 35(B), the rising edge is delayed by R_PG1 + R_PG2 and C_PG, while the falling edge is delayed a lesser amount by R_PG2 and C_PG. Adding a diode across R_PG2 (Figure 35(C)) allows for equal delays at the two edges, or a short delay at the rising edge and a long delay at the falling edge.

Figure 33. Programming the PGD Threshold

Figure 34. Power Good Output

Figure 35. Adding Delay to the Power Good Output Pin

TI recommends to set the PG threshold 5% below the minimum input voltage to ensure that the PG is asserted under all input voltage conditions. For this example, PGDH of 38 V and PGDL of 35 V is targeted. R5 and R6 are computed using the following equations:

Equation 39.

Equation 40.

Nearest available 1% resistors should be chosen. Set R5 = 150 kΩ and R6 = 10.5 kΩ.

10.2.1.2.8 Input and Output Protection

Proper operation of the LM5066 hot swap circuit requires a voltage clamping element present on the supply side of the connector into which the hot swap circuit is plugged in. A TVS is ideal, as depicted in . The TVS is necessary to absorb the voltage transient generated whenever the hot swap circuit shuts off the load current. This effect is the most severe during a hot-short when a large current is suddenly interrupted when the FET shutts off. The TVS should be chosen to have minimal leakage current at V_IN,MAX and to clamp the voltage to under 100V during hot-short events. For many high power applications 5.0SMDJ60A is a good choice.

If the load powered by the LM5066 hot swap circuit has inductive characteristics, a Schottky diode is required across the LM5066’s output, along with some load capacitance. The capacitance and the diode are necessary to limit the negative excursion at the OUT pin when the load current is shut off.

Figure 36. Output Diode Required for Inductive Loads

10.2.1.2.9 Final Schematic and Component Values

Figure 28 shows the schematic used to implement the requirements described in the previous section. In addition, Table 47 provides the final component values that were used to meet the design requirements for a 48-V, 10-A hotswap design. The application curves in the next section are based on these component values.