SNVS628H October   2009  – December 2019 LM5060

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Typical Application Circuit
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-Up Sequence
      2. 7.4.2 Status Conditions
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Gate Control
      2. 8.1.2  Fault Timer
      3. 8.1.3  VGS Considerations
      4. 8.1.4  VDS Fault Condition
      5. 8.1.5  Overcurrent Fault
      6. 8.1.6  Restart After Overcurrent Fault Event
      7. 8.1.7  Enable
      8. 8.1.8  UVLO
      9. 8.1.9  OVP
      10. 8.1.10 Restart After OVP Event
      11. 8.1.11 nPGD Pin
    2. 8.2 Typical Applications
      1. 8.2.1 Example Number 1: LM5060EVAL Design
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 VDS Fault Detection and Selecting Sense Pin Resistor RS
          2. 8.2.1.2.2 Turn-On Time
          3. 8.2.1.2.3 Fault Detection Delay Time
          4. 8.2.1.2.4 MOSFET Selection
          5. 8.2.1.2.5 Input and Output Capacitors
          6. 8.2.1.2.6 UVLO, OVP
          7. 8.2.1.2.7 POWER GOOD Indicator
          8. 8.2.1.2.8 Input Bypass Capacitor
          9. 8.2.1.2.9 Large Load Capacitance
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Example Number 2: Reverse Polarity Protection With Diodes
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Application Curve
      3. 8.2.3 Example Number 3: Reverse Polarity Protection With Resistor
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
          1. 8.2.3.2.1 Reverse Polarity Protection With a Resistor
          2. 8.2.3.2.2 Fault Detection With RS and RO
        3. 8.2.3.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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Fault Detection Delay Time

To allow the gate of the MOSFET adequate time to change, and to allow the MOSFET to conduct currents beyond the protection threshold for a brief period of time, a fault delay timer function is provided. This feature is important when drive loads which require a surge of current in excess of the normal ON current upon start up, or at any point in time, such as lamps and motors. A single low leakage capacitor (CTIMER) connected from the TIMER (pin 7), to ground sets the delay time interval for both the VGS status detection at start-up and for the subsequent VDS Over-Current fault detection.

When the LM5060 is enabled under normal operating conditions the timer capacitor will begin charging at a 6 μA (typical) rate while simultaneously charging the gate of the external MOSFET at a 24 μA (typical) rate. The gate-to-source voltage (VGS) of the external MOSFET is expected to reach the 5-V (typical) threshold before the timer capacitor has charged to the VTMRH threshold (2 V typical) in order to avoid being shutdown.

While VGS is less than the typical 5-V threshold (VGATE-TH), the VDS start-up fault delay time is calculated from:

Equation 3. LM5060 30104254.gif

where

  • ITMRL is typically 6 μA and VTMRH is typically 2 V

If the CTIMER value is 68 nF (0.068μF) the VGS start-up fault delay time would typically be:

Equation 4. VDS Fault Delay = ((2 V x 0.068 μF) / 6 μA) = 23 ms

When the LM5060 has successfully completed the start-up sequence by reaching a VGS of 5 V within the fault delay time set by the timer capacitor (CTIMER), the capacitor is quickly discharged to 300 mV (typical) and the charge current is increased to 11 μA (typical) while the gate of the external MOSFET is continued to be charge at a 24 μA (typical) rate. The external MOSFET may not be fully enhanced at this point in time and some additional time may be needed to allow the gate-to-source voltage (VGS) to charge to a higher value. The drain-to-source voltage (VDS) of the external MOSFET must fall below the VDSTH threshold set by RS and ISENSE before the timer capacitor has charged to the VTMRH threshold (2 V typical) to avoid a fault.

When VGS is greater than the typical 5-V threshold (VGATE-TH), the VDS transition fault delay time is calculated from:

Equation 5. LM5060 30104255.gif

where

  • ITMRH is typically 11 μA
  • VTMRH is typically 2 V
  • VTMRL is typically 300 mV

If the CTIMER value is 68 nF(0.068 μF) the VDS transition fault delay time would typically be:

Equation 6. VDS Fault Delay = (((2 V–0.3 V) x 0.068 μF) / 11 μA) = 10 ms

Should a subsequent load current surge trip the VDS Fault Comparator, the timer capacitor discharge transistor turns OFF and the 11 μA (typical) current source begins linearly charging the timer capacitor. If the surge current, with the detected excessive VDS voltage, lasts long enough for the timer capacitor to charge to the timing comparator threshold (VTMRH) of typically 2 V, the LM5060 will immediately discharge the MOSFET gate and latch the MOSFET off. The VDS fault delay time during an Over-Current event is calculated from:

Equation 7. LM5060 30104256.gif

where

  • ITMRH is typically 11 μA
  • VTMRH is typically 2 V

If the CTIMER value is 68 nF(0.068 μF) the VDS Over-Current fault delay time would typically be:

Equation 8. VDS Fault Delay = ((2 V x 0.068 μF) / 11 μA) = 12 ms

Since a single capacitor is used to set the delay time for multiple fault conditions, it is likely that some compromise will need to be made between a desired delay time and a practical delay time.