SNVS363E August   2005  – November 2015 LM5026

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High Voltage Start-Up Regulator
      2. 7.3.2  Line Undervoltage Detector
      3. 7.3.3  PWM Outputs
      4. 7.3.4  Gate Driver Outputs
      5. 7.3.5  PWM Comparator/Slope Compensation
      6. 7.3.6  Maximum Duty Cycle Clamp
      7. 7.3.7  Soft-Start / Soft-Stop
      8. 7.3.8  Current Sense and Current Limit
      9. 7.3.9  Overload Protection Timer
      10. 7.3.10 Oscillator and Sync Capability
      11. 7.3.11 Thermal Protection
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Line Input (VIN)
      2. 8.1.2 For Application > 100 V
      3. 8.1.3 Undervoltage Lockout (UVLO)
      4. 8.1.4 Oscillator (RT, SYNC)
      5. 8.1.5 Voltage Feedback (COMP)
      6. 8.1.6 Current Sense (CS)
      7. 8.1.7 Hiccup Mode Current Limit Restart (RES)
      8. 8.1.8 Soft-Start (SS)
      9. 8.1.9 Voltage-Dependent Maximum Duty Cycle
        1. 8.1.9.1 Programmable Maximum Duty Cycle Clamp (DCL)
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Determine VIN Configuration
        2. 8.2.2.2 Determine UVLO Configuration
        3. 8.2.2.3 Configure Operating Frequency
        4. 8.2.2.4 Configure Hiccup Mode and Soft Start
        5. 8.2.2.5 Determine Deadtime and Maximum Duty Cycle
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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订购信息

5 Pin Configuration and Functions

PW Package
16-Pin TSSOP
Top View
LM5026 20147902.gif
NHQ Package
16-Pin WSON
Top View
LM5026 20147950.gif

Pin Functions

PIN TYPE(1) DESCRIPTION
NO. NAME
1 VIN I Input voltage source. Input to the start-up regulator. Operating input range is 13 V to 100 V with transient capability to 105 V. For power sources outside of this range, the LM5026 can be biased directly at VCC by an external regulator.
2 UVLO I Line undervoltage lockout. An external voltage divider from the power source sets the shutdown and standby comparator levels. When UVLO reaches the 0.4-V threshold the VCC and REF regulators are enabled. At the 1.25-V threshold the SS pin is released and the device enters the active mode.
3 CS I Current Sense input for current mode control and current limit. If CS exceeds 0.5 V, the output pulse will be terminated, entering cycle-by-cycle current limit. An internal switch holds CS low for 100 nS after OUT_A switches high to blank leading edge transients.
4 RES I Restart Timer. If cycle-by-cycle current limit is reached during any cycle, a 10-µA current is sourced to the RES pin capacitor. If the RES capacitor voltage reaches 2.5 V, the soft-start capacitor will be fully discharged and then released with a pullup current of 1 µA. After the first output pulse at OUT_A (when SS = 1.4 V), the SS pin charging current will revert back to 50 µA.
5 TIME I Gate drive overlap or deadtime control. An external resistor (RSET) sets either the overlap time or deadtime for the active clamp output. An RSET resistor connected between TIME and AGND produces in-phase OUT_A and OUT_B pulses with overlap. An RSET resistor connected between TIME and REF produces out-of-phase OUT_A and OUT_B pulses with deadtime.
6 REF O Output of 5-V reference. Maximum output current is 10 mA. Locally decouple with a 0.1-µF capacitor.
7 VCC P Output of the high voltage start-up regulator. The VCC voltage is regulated to 7.6 V. If an auxiliary winding raises the voltage on this pin above the regulation setpoint, the internal start-up regulator will shutdown, thus reducing the IC power dissipation.
8 OUT_A O Main output driver. Output of the main switch PWM gate driver. Capable of 3-A peak sink current.
9 OUT_B O Active clamp output driver. Output of the active clamp switch gate driver. Capable of 0.5-A peak source and sink current.
10 PGND G Power ground. Connect directly to analog cround.
11 AGND G Analog return. Connect directly to power cround.
12 SS I Soft-start. An external capacitor and an internal 50-µA current source set the soft-start ramp. The SS current source is reduced to 1 µA following a restart event. The soft-stop discharge current is 50 µA.
13 COMP I Input to the pulse width modulator. The external optocoupler connected to the COMP pin sources current into an internal NPN current mirror. The PWM duty cycle is maximum with zero input current, while 1 mA reduces the duty cycle to zero. The current mirror improves the frequency response by reducing the ac voltage across the optocoupler detector.
14 RT I Oscillator frequency control. Normally biased at 2 V. The total external resistance connected between RT and AGND sets the internal oscillator frequency.
15 SYNC I/O Oscillator synchronization input/output. The internal oscillator can be synchronized to an external clock with an external pulldown device. Multiple LM5026 devices can be synchronized together by connection of their SYNC pins.
16 DCL I Maximum duty cycle control. An external resistor divider connected from RT to AGND sets the maximum output duty cycle for OUT_A.
EP Exposed Pad (WSON Package Only) G Exposed Pad, underside of WSON package. Connect to system ground plane for reduced thermal resistance.
(1) P = Power, G = Ground, I = Input, O = Output, I/O = Input/Output