ZHCSE20B July 2015 – November 2017 LM46001-Q1
PRODUCTION DATA.
The LM46001-Q1 integrates an internal LDO to generate VCC for control circuitry and MOSFET drivers. The nominal voltage for VCC is 3.3 V. The VCC pin is the output of the LDO and must be properly bypassed. A high quality ceramic capacitor with 2.2 µF to 10 µF capacitance and 6.3 V or higher rated voltage should be placed as close as possible to VCC and grounded to the exposed PAD and ground pins. The VCC output pin should not be loaded, left floating, connected to any other external supply, or shorted to ground during operation. Shorting VCC to ground during operation may cause damage to the LM46001-Q1.
Under voltage lockout (UVLO) prevents the LM46001-Q1 from operating until the VCC voltage exceeds 3.14 V (typical). The VCC UVLO threshold has 567 mV of hysteresis (typically) to prevent undesired shuting down due to temperary VIN droops.
The internal LDO has two inputs: primary from VIN and secondary from BIAS input. The BIAS input powers the LDO when VBIAS is higher than the change-over threshold. Power loss of an LDO is calculated by ILDO * (VIN-LDO - VOUT-LDO). The higher the difference between the input and output voltages of the LDO, the more power loss occur to supply the same output current. The BIAS input is designed to reduce the difference of the input and output voltages of the LDO to reduce power loss and improve the LM46001-Q1 efficiency, especially at light load. It is recommended to tie the BIAS pin to VOUT when VOUT ≥ 3.3 V. The BIAS pin should be grounded in applications with VOUT less than 3.3 V. BIAS input can also come from an external voltage source, if available, to reduce power loss. When used, TI recommends a 1-µF to 10-µF high-quality ceramic capacitor to bypass the BIAS pin to ground.