ZHCSDR3C 数据表 | 德州仪器 TI.com.cn

6.1 Absolute Maximum Ratings

over the recommended operating junction temperature (T_J) range of -40°C to +125°C⁽¹⁾

	PARAMETER	MIN	MAX	UNIT
Input voltages	VIN to PGND	–0.3	42⁽²⁾	V
	EN to PGND	–0.3	V_IN + 0.3
	FB, RT, SS/TRK to AGND	–0.3	3.6
	PGOOD to AGND	–0.3	15
	SYNC to AGND	–0.3	5.5
	BIAS to AGND	–0.3	30 or V_IN⁽³⁾
	AGND to PGND	–0.3	0.3
Output voltages	SW to PGND	–0.3	V_IN + 0.3	V
	SW to PGND less than 10-ns transients	–3.5	42
	CBOOT to SW	–0.3	5.5
	VCC to AGND	–0.3	3.6
Storage temperature, T_stg		–65	150	°C
Operating junction temperature		–40	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) At maximum duty cycle 0.01%

(3) Whichever is lower

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per AEC Q100-002⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per AEC Q100-011	±750	V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over the recommended operating junction temperature (T_J) range of –40°C to +125°C ⁽¹⁾

	PARAMETER	MIN	MAX	UNIT
Input voltages	VIN to PGND	3.5	36	V
	EN	–0.3	V_IN
	FB	–0.3	1.1
	PGOOD	–0.3	12
	BIAS input not used	–0.3	0.3
	BIAS input used	3.3	28 or V_IN ⁽²⁾
	AGND to PGND	–0.1	0.1
Output voltage	V_OUT	1	28	V
Output current	I_OUT	0	3	A
Temperature	Operating junction temperature, T_J	–40	125	°C

(1) Recommended Operating Conditions indicates conditions for which the device is intended to be functional, but do not ensure specific performance limits. For verified specifications, see Electrical Characteristics.

(2) Whichever is lower.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾⁽²⁾⁽³⁾		LM43603-Q1	UNIT
		PWP (HTSSOP)
		16 PINS
R_θ_JA	Junction-to-ambient thermal resistance	38.9⁽⁴⁾	°C/W
R_θ_{JC (Top)}	Junction-to-case (top) thermal resistance	24.3	°C/W
R_θ_JB	Junction-to-board thermal resistance	19.9	°C/W
ψ_JT	Junction-to-top characterization parameter	0.7	°C/W
ψ_JB	Junction-to-board characterization parameter	19.7	°C/W
R_θ_JC(bot)	Junction-to-case (bottom) thermal resistance	1.7	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

(2) The package thermal impedance is calculated in accordance with JESD 51-7;

(3) Thermal resistances were simulated on a 4 layer, JEDEC board.

(4) See Figure 98 for R_θJA vs Copper Area Curve

6.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature (T_J) range of –40°C to +125°C, unless otherwise stated. Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at T_J = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: V_IN = 12 V, V_OUT = 3.3 V, F_S = 500 kHz.

PARAMETER		CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY VOLTAGE (VIN PIN)
V_IN-MIN-ST	Minimum input voltage for start-up				3.8	V
I_SHDN	Shutdown quiescent current	V_EN = 0 V		1.2	3.1	µA
I_Q-NONSW	Operating quiescent current (non-switching) from V_IN	V_EN = 3.3 V V_FB= 1.5 V V_BIAS = 3.4 V external		5	10	µA
I_BIAS-NONSW	Operating quiescent current (non-switching) from external V_BIAS	V_EN = 3.3 V V_FB= 1.5 V V_BIAS = 3.4 V external		85	130	µA
I_Q-SW	Operating quiescent current (switching)	V_EN = 3.3 V I_OUT= 0 A R_T = open V_BIAS = V_OUT= 3.3 V R_FBT = 1 Meg		27		µA
ENABLE (EN PIN)
V_EN-VCC-H	Voltage level to enable the internal LDO output V_CC	V_ENABLE high level	1.2			V
V_EN-VCC-L	Voltage level to disable the internal LDO output V_CC	V_ENABLE low level			0.525	V
V_EN-VOUT-H	Precision enable level for switching and regulator output: V_OUT	V_ENABLE high level	2	2.20	2.42	V
V_EN-VOUT-HYS	Hysteresis voltage between V_OUT precision enable and disable thresholds	V_ENABLE hysteresis		–290		mV
I_LKG-EN	Enable input leakage current	V_EN = 3.3 V		0.85	1.75	µA
INTERNAL LDO (VCC and BIAS PINS)
V_CC	Internal LDO output voltage V_CC	V_IN ≥ 3.8 V		3.28		V
V_CC-UVLO	Undervoltage lockout (UVLO) thresholds for V_CC	V_CC rising threshold		3.1		V
V_CC-UVLO	Undervoltage lockout (UVLO) thresholds for V_CC	Hysteresis voltage between rising and falling thresholds		–520		mV
V_BIAS-ON	Internal LDO input change over threshold to BIAS	V_BIAS rising threshold		2.94	3.18	V
V_BIAS-ON	Internal LDO input change over threshold to BIAS	Hysteresis voltage between rising and falling thresholds		-75		mV
VOLTAGE REFERENCE (FB PIN)
V_FB	Feedback voltage	T_J = 25 ºC	1.012	1.015	1.019	V
V_FB	Feedback voltage	T_J = -40 ºC to 125 ºC	0.999	1.015	1.032	V
I_LKG-FB	Input leakage current at FB pin	FB = 1.015 V		0.2	65	nA
THERMAL SHUTDOWN
T_SD ⁽¹⁾	Thermal shutdown	Shutdown threshold		160		ºC
T_SD ⁽¹⁾	Thermal shutdown	Recovery threshold		150		ºC
CURRENT LIMIT AND HICCUP
I_HS-LIMIT	Peak inductor current limit		4.4	5.5	6.4	A
I_LS-LIMIT	Inductor current valley limit		2.6	3	3.3	A
SOFT START (SS/TRK PIN)
I_SSC	Soft-start charge current		1.25	2	2.75	µA
R_SSD	Soft-start discharge resistance	UVLO, TSD, OCP, or EN = 0 V		18		kΩ
POWER GOOD (PGOOD PIN)
V_PGOOD-HIGH	Power-good flag over voltage tripping threshold	% of FB voltage		110%	113%
V_PGOOD-LOW	Power-good flag under voltage tripping threshold	% of FB voltage	77%	88%
V_PGOOD-HYS	Power-good flag recovery hysteresis	% of FB voltage		6%
R_PGOOD	PGOOD pin pulldown resistance when power bad	V_EN = 3.3 V		69	150	Ω
R_PGOOD	PGOOD pin pulldown resistance when power bad	V_EN = 0 V		150	350	Ω
MOSFETS ⁽²⁾
R_DS-ON-HS	High-side MOSFET ON-resistance	I_OUT = 1 A V_BIAS = V_OUT = 3.3 V		120		mΩ
R_DS-ON-LS	Low-side MOSFET ON-resistance	I_OUT = 1 A V_BIAS = V_OUT = 3.3 V		65		mΩ

(1) Ensured by design

(2) Measured at pins

6.6 Timing Requirements

		NOM	UNIT
CURRENT LIMIT AND HICCUP
N_OC	Hiccup wait cycles when LS current limit tripped	32	Cycles
T_OC	Hiccup retry delay time	5.5	ms
SOFT START (SS/TRK PIN)
T_SS	Internal soft-start time when SS pin open circuit	4.1	ms
POWER GOOD (PGOOD PIN)
T_PGOOD-RISE	Power-good flag rising transition deglitch delay	220	µs
T_PGOOD-FALL	Power-good flag falling transition deglitch delay	220	µs

6.7 Switching Characteristics

Limits apply over the recommended operating junction temperature (T_J) range of –40°C to +125°C, unless otherwise stated. Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at T_J = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: V_IN = 12 V, V_OUT = 3.3 V, F_S = 500 kHz.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SW (SW PIN)
t_ON-MIN⁽¹⁾	Minimum high side MOSFET ON time			125	165	ns
t_OFF-MIN⁽¹⁾	Minimum high side MOSFET OFF time			200	250	ns
OSCILLATOR (SW and SYNC PINS)
F_OSC-DEFAULT	Oscillator default frequency	RT pin open circuit	425	500	580	kHz
F_ADJ	Minimum adjustable frequency	With 1% resistors at RT pin		200		kHz
	Maximum adjustable frequency			2200		kHz
	Frequency adjust accuracy			10%
V_SYNC-HIGH	Sync clock high level threshold		2			V
V_SYNC-LOW	Sync clock low level threshold				0.4	V
D_SYNC-MAX	Sync clock maximum duty cycle			90%
D_SYNC-MIN	Sync clock minimum duty cycle			10%
T_SYNC-MIN	Mininum sync clock ON and OFF time			80		ns

(1) Ensured by design

6.8 Typical Characteristics

Unless otherwise specified, V_IN = 12 V, V_OUT = 3.3 V, F_S = 500 kHz, L = 6.8 µH and room temperature. See Application Performance Curves for bill of materials for other V_OUT and F_S combinations.