ZHCSCC4D November 2013 – March 2019 LM3697
PRODUCTION DATA.
| MIN | NOM | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| I2C-COMPATIBLE TIMING SPECIFICATIONS (SCL, SDA)(1) | ||||||
| t1 | SCL (clock period) | 2.7 V ≤ VIN ≤ 5.5 V | 2.5 | µs | ||
| t2 | Data In set-up time to SCL high | 2.7 V ≤ VIN ≤ 5.5 V | 100 | ns | ||
| t3 | Data out stable after SCL low | 2.7 V ≤ VIN ≤ 5.5 V | 0 | ns | ||
| t4 | SDA low set-up time to SCL low (start) | 2.7 V ≤ VIN ≤ 5.5 V | 100 | ns | ||
| t5 | SDA high hold time after SCL high (stop) | 2.7 V ≤ VIN ≤ 5.5 V | 100 | ns | ||
| INTERNAL POR THRESHOLD AND HWEN TIMING SPECIFICATION | ||||||
| VPOR | POR reset release voltage threshold | VIN ramp time = 100 µs | 1.7 | 2.1 | V | |
| VIN ramp time = 100 µs, TA = 25°C | 1.9 | |||||
| tHWEN | First I2C start pulse after HWEN high | 2.7 V ≤ VIN ≤ 5.5 V, POR reset complete | 20 | µs | ||
| POR reset complete, TA = 25°C | 5.0 | |||||
Figure 1. I2C-Compatible Interface Timing