SNVS834 August   2014 LM3631

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Timing Requirements (SDA, SCL)
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Features Description
      1. 8.3.1  Backlight
        1. 8.3.1.1 Backlight Brightness Control
          1. 8.3.1.1.1 LED Current With Brightness Selection '00'
          2. 8.3.1.1.2 LED Current With Brightness Selection '01'
          3. 8.3.1.1.3 LED Current With Brightness Selections '10' and '11'
        2. 8.3.1.2 Linear Slope and Advanced Slope
        3. 8.3.1.3 Mapper
        4. 8.3.1.4 PWM Detector and PWM Input
      2. 8.3.2  Backlight Boost Converter
        1. 8.3.2.1 Headroom Voltage
        2. 8.3.2.2 Automatic Switching Frequency Shift
        3. 8.3.2.3 Inductor Select Bit
        4. 8.3.2.4 PI-Compensator
      3. 8.3.3  Backlight Protection and Faults
        1. 8.3.3.1 Overvoltage Protection (OVP) and Open-Load Fault Protection
        2. 8.3.3.2 Overcurrent Protection (OCP) and Overcurrent Protection Fault
          1. 8.3.3.2.1 Overcurrent Protection Fault Flag (BL_OCPFLT)
          2. 8.3.3.2.2 Short Circuit Fault Flag (BL_SCFLT)
      4. 8.3.4  LCD Bias
        1. 8.3.4.1 Display Bias Power (VPOS, VNEG, VOREF)
        2. 8.3.4.2 Display Bias Power Sequencing (VPOS, VNEG, VOREF, VCONT)
          1. 8.3.4.2.1 Start-Up and Shutdown Delays
          2. 8.3.4.2.2 Special Conditions During Display Bias Power Sequencing
        3. 8.3.4.3 Active Discharge
        4. 8.3.4.4 LCD Bias Protection
      5. 8.3.5  Display Controller Power (VLDO_CONT)
      6. 8.3.6  RESET Register
      7. 8.3.7  nRST Input
      8. 8.3.8  FLAG Pin
      9. 8.3.9  Power-Good Flag
      10. 8.3.10 OTP_SEL Pin
      11. 8.3.11 Thermal Shutdown
      12. 8.3.12 Undervoltage Lockout
    4. 8.4 Device Functional Modes
      1. 8.4.1 Modes of Operation
    5. 8.5 Programming
      1. 8.5.1 I2C-Compatible Serial Bus Interface
        1. 8.5.1.1 Interface Bus Overview
        2. 8.5.1.2 Data Transactions
        3. 8.5.1.3 Acknowledge Cycle
        4. 8.5.1.4 Acknowledge After Every Byte Rule
        5. 8.5.1.5 Addressing Transfer Formats
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 External Components
        2. 9.2.2.2 Inductor Selection
        3. 9.2.2.3 Boost Output Capacitor Selection
        4. 9.2.2.4 Backlight Boost Diode Selection
        5. 9.2.2.5 Charge Pump Capacitor Selection
        6. 9.2.2.6 LDO Output Capacitor Selection
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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订购信息

6 Pin Configuration and Functions

DSBGA
24 BUMPS
LM3631_Pin_Assignment.gif

Pin Functions

PIN DESCRIPTION
NUMBER NAME
A1 CP_VNEG Negative LCD bias supply voltage. Can be left unconnected if charge pump is disabled.
A2 C2 Inverting charge pump flying capacitor negative pin. Can be left unconnected if charge pump is disabled.
A3 PGND Power ground connection for boost converters and charge pump.
A4 C1 Inverting charge pump flying capacitor positive pin. Can be left unconnected if charge pump is disabled.
B1 LDO_OREF LDO_OREF output voltage. Can be left unconnected if LDO is disabled.
B2 PWM PWM input for brightness control. Must be connected to GND if not used.
B3 SDA Serial data connection for I2C-compatible interface. Must be pulled high to VDDIO if not used.
B4 BST_OUT LCD bias boost output voltage. Internally connected to the input of CP_VNEG, LDO_VPOS, and LDO_OREF.
C1 LDO_VPOS Positive LCD bias supply rail. Can be left unconnected if LDO is disabled.
C2 LDO_CONT Positive supply voltage for display panel controller. Can be left unconnected if disabled.
C3 SCL Serial clock connection for I2C-compatible interface. Must be pulled high to VDDIO if not used.
C4 BST_SW LCD bias boost switch pin.
D1 AGND Analog ground connection for control circuitry.
D2 OTP_SEL Default setting selection. Must be tied to GND or to VDDIO.
D3 FLAG Programmable interrupt flag. Open drain output. Can be left unconnected if not used.
D4 GND_BST_SW LCD bias boost and inverting charge pump ground connection.
E1 LED2 Input pin to internal LED current sink 2. Can be left unconnected if not used.
E2 LCD_EN LCD enable input. Logic high turns on LCD bias voltages and backlight per sequencing settings.
E3 nRST Active low reset input.
E4 VIN Input voltage connection. Connect to 2.7-V to 5-V supply voltage.
F1 LED1 Input pin to internal LED current sink 1. Can be left unconnected if not used.
F2 VOUT Backlight boost output voltage. Output capacitor is connected to this pin.
F3 SW Backlight boost switch pin.
F4 GND_SW Backlight boost ground connection.