ZHCSBI0C March   2013  – October 2014 LM3279

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 System Characteristics
    7. 6.7 System Characteristics Recommended Capacitance Specifications
    8. 6.8 Typical Performance Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Dynamically Adjustable Output Voltage
      2. 7.3.2  Seamless Mode Transition
      3. 7.3.3  Setting The Output Voltage
      4. 7.3.4  General Purpose Outputs
      5. 7.3.5  VCONON
      6. 7.3.6  RDSON Management
      7. 7.3.7  Supply Current Limit
      8. 7.3.8  Reverse Current Limit
      9. 7.3.9  VCON Overvoltage Clamp
      10. 7.3.10 Thermal Overload Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable And Shutdown Mode
      2. 7.4.2 Low-Power Mode
      3. 7.4.3 Standby Mode
      4. 7.4.4 PFM Mode
    5. 7.5 Programming
      1. 7.5.1 Digital Control Serial Bus Interface
      2. 7.5.2 Supported Command Sequences
      3. 7.5.3 Device Enumeration
      4. 7.5.4 I/O
      5. 7.5.5 Control Interface Timing Parameters
    6. 7.6 Registers
      1. 7.6.1 Programmable Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Typical Application Circuit: Digital Control
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Output Current Capability
          2. 8.2.1.2.2 Recommended External Components
            1. 8.2.1.2.2.1 Inductor Selection
            2. 8.2.1.2.2.2 Input Capacitor Selection
          3. 8.2.1.2.3 Output Capacitor Selection
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Typical Application Circuit: Analog Control
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB
        1. 10.1.1.1 Energy Efficiency
        2. 10.1.1.2 EMI
    2. 10.2 Layout Examples
      1. 10.2.1 LM3279 RF Evaluation Board
      2. 10.2.2 Component Placement
    3. 10.3 DSBGA Package Assembly And Use
    4. 10.4 Manufacturing Considerations
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 文档支持
      1. 11.2.1 相关文档　
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

DSBGA
16 Pins
LM3279 30173303.gif

Pin Functions

PIN TYPE DESCRIPTION
NUMBER NAME
A1 SCLK IN Digital control interface (DCON) RFFE Bus clock input. Typically connected to RFFE master on RF or Baseband IC. SCLK must be held low when VIO is not applied.
B1 SDATA I/O Digital control interface (DCON) RFFE Bus data input/output. Typically connected to RFFE master on RF or Baseband IC. SDATA must be held low when VIO is not applied.
C1 VIO IN Digital control interface (DCON) 1.8-V supply input. VIO functions as the RFFE interface reference voltage. VIO also functions as a reset and enable input to LM3279. Bypass capacitor should be connected between VIO and GND. Typically connected to voltage regulator controlled by RF or Baseband IC. When VIO = HIGH, EN shall be connected to GND.
D1 GND Ground Digital Ground.
A2 GPO0 I/O Multipurpose GPIO. When VIO = HIGH, GPO0 is a general purpose output for configuring RF front end circuitry. When the GPO0 control bit in Register 02 is set to 1, the output is driven to a 1.8-V (VIO) high logic level. The output is pulled to a low logic level when the GPO0 control bit is set to 0. (Input has an internal pull-up resistor.)
B2 VCON IN Voltage Control Analog input. When EN = HIGH, VCON controls the output voltage in PWM and PFM modes. When in Digital control, VCON can be left as no connect or connected to system ground.
C2 FB Ground Feedback input to inverting input of error amplifier. Connect output voltage directly to this node at load point.
D2 VOUT PWR Regulated output voltage of LM3279. Connect this to a 10-µF ceramic output filter capacitor to GND.
A3 GPO1 I/O Multipurpose GPIO. When VIO = HIGH, GPO1 is a general purpose output for configuring RF front end circuitry. When the GPO1 control bit in Register 02 is set to 1, the output is driven to a 1.8-V (VIO) high logic level. The output is pulled to a low logic level when the GPO1 control bit is set to 0. (Input has an internal pull-up resistor.)
B3 EN IN Enable Pin. Pulling this pin higher than 1.2 V enables part to function in analog control mode. VIO must be tied to ground.
C3 SGND Ground Signal Ground for analog circuits and control circuitry.
D3 SW2 PWR Switch pin for Internal Power Switches M3 and M4. Connect inductor between SW1 and SW2.
A4 SVIN PWR SVIN is no connect. Analog supply is internally connected to PVIN.
B4 PVIN PWR Power MOSFET input and power current input pin. Optional low-pass filtering may help reduce radiated EMI and noise during buck and buck-boost modes.
C4 SW1 PWR Switch pin for Internal Power Switches M1 and M2. Connect inductor between SW1 and SW2.
D4 PGND Ground Power Ground for Power MOSFETs and gate drive circuitry.