ZHCSOZ8A april   2023  – august 2023 LM2103

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Start-Up and UVLO
      2. 7.3.2 Input Stages
      3. 7.3.3 Level Shift
      4. 7.3.4 Output Stages
      5. 7.3.5 SH Transient Voltages Below Ground
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Select External Bootstrap Diode and Its Series Resistor
        2. 8.2.2.2 Select Bootstrap and GVDD Capacitor
        3. 8.2.2.3 Select External Gate Driver Resistor
        4. 8.2.2.4 Estimate the Driver Power Loss
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 第三方产品免责声明
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 接收文档更新通知
    4. 11.4 支持资源
    5. 11.5 Trademarks
    6. 11.6 静电放电警告
    7. 11.7 术语表
  13. 12Mechanical, Packaging, and Orderable Information

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6.6 Switching Characteristics

VGVDD = VBST = 12 V, GND = VSH = 0 V, No Load on GL or GH, TJ = 25°C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PROPAGATION DELAYS
tDLRF VINL rising to VGL falling VINL = 0 V to 3 V, CLOAD = 0 pF. Time from 50% of the input to 90% of the output. 115 ns
tDHFF VINH falling to VGH falling VINH = 3 V to 0 V, CLOAD = 0 pF. Time from 50% of the input to 90% of the output. 115 ns
tDLFR VINL falling to VGL rising VINL = 3 V to 0 V, CLOAD = 0 pF. Time from 50% of the input to 10% of the output. 115 ns
tDHRR VINH rising to VGH rising VINH = 0 V to 3 V, CLOAD = 0 pF. Time from 50% of the input to 10% of the output. 115 ns
DEADTIME
tDT Internal Deadtime 475 ns
OUTPUT RISE AND FALL TIME
tR_GL GL CLOAD = 1000 pF 28 ns
tR_GH GH CLOAD = 1000 pF 28 ns
tF_GL GL CLOAD = 1000 pF 18 ns
tF_GH GH CLOAD = 1000 pF 18 ns