ZHCSE62A July   2015  – September 2015 ISO7831

PRODUCTION DATA.  

  1. 特性
  2. 应用范围
  3. 说明
  4. 修订历史记录
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Rating
    6. 6.6  Electrical Characteristics, 5 V
    7. 6.7  Electrical Characteristics, 3.3 V
    8. 6.8  Electrical Characteristics, 2.5 V
    9. 6.9  Switching Characteristics, 5 V
    10. 6.10 Switching Characteristics, 3.3 V
    11. 6.11 Switching Characteristics, 2.5 V
    12. 6.12 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 High Voltage Feature Description
        1. 8.3.1.1 Package Insulation and Safety-Related Specifications
        2. 8.3.1.2 Insulation Characteristics
        3. 8.3.1.3 IEC 60664-1 Ratings Table
        4. 8.3.1.4 Regulatory Information
        5. 8.3.1.5 Safety Limiting Values
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device I/O Schematics
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Electromagnetic Compatibility (EMC) Considerations
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Material
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档
    2. 12.2 相关链接
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • DWW|16
  • DW|16
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Specifications

6.1 Absolute Maximum Ratings

See (1)
MIN MAX UNIT
VCC1,
VCC2
Supply voltage(2) –0.5 6 V
Voltage INx –0.5 VCCX + 0.5(3) V
OUTx
ENx
IO Output current –15 15 mA
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak voltage values.
(3) Maximum voltage must not exceed 6 V

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±6000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VCC1, VCC2 Supply voltage 2.25 5.5 V
IOH High-level output current VCCO(2) = 5 V –4 mA
VCCO(2) = 3.3 V –2
VCCO(2) = 2.5 V –1
IOL Low-level output current VCCO(2) = 5 V 4 mA
VCCO(2) = 3.3 V 2
VCCO(2) = 2.5 V 1
VIH High-level input voltage 0.7 × VCCI (2) VCCI (2) V
VIL Low-level input voltage 0 0.3 × VCCI(2) V
DR Signaling rate 0 100 Mbps
TJ Junction temperature(1) –55 150 °C
TA Ambient temperature –55 25 125 °C
(1) To maintain the recommended operating conditions for TJ, see Thermal Information.
(2) VCCI = Input-side VCC; VCCO = Output-side VCC.

6.4 Thermal Information

THERMAL METRIC(1) DW (SOIC) UNIT
16 Pins
RθJA Junction-to-ambient thermal resistance 78.9 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 41.6
RθJB Junction-to-board thermal resistance 43.6
ψJT Junction-to-top characterization parameter 15.5
ψJB Junction-to-board characterization parameter 43.1
RθJC(bottom) Junction-to-case(bottom) thermal resistance N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Power Rating

VALUE UNIT
PD Maximum power dissipation by ISO7831 VCC1 = VCC2 = 5.5 V, TJ = 150°C,
CL = 15 pF, input a 50 MHz 50% duty cycle square wave
150 mW
PD1 Maximum power dissipation by side-1 of ISO7831 50
PD2 Maximum power dissipation by side-2 of ISO7831 100

6.6 Electrical Characteristics, 5 V

VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = –4 mA; see Figure 7 VCCO(1) – 0.4 VCCO(1) – 0.2 V
VOL Low-level output voltage IOL = 4 mA; see Figure 7 0.2 0.4 V
VI(HYS) Input threshold voltage hysteresis 0.1 × VCCO(1) V
IIH High-level input current VIH = VCCI(1) at INx or ENx 10 μA
IIL Low-level input current VIL = 0 V at INx or ENx –10 μA
CMTI Common-mode transient immunity VI = VCCI(1) or 0 V; see Figure 10 70 100 kV/μs
ICC1 Supply current Disable;
EN1 = EN2 = 0 V
DC signal: VI = 0 V (Devices with suffix F) , VI = VCCI (Devices without suffix F) 1.0 1.6 mA
ICC2 Disable;
EN1 = EN2 = 0 V
DC signal: VI = 0 V (Devices with suffix F) , VI = VCCI (Devices without suffix F) 0.8 1.3
ICC1 Disable;
EN1 = EN2 = 0 V
DC signal: VI = VCCI (Devices with suffix F) , VI = 0 V(Devices without suffix F) 3.3 4.8
ICC2 Disable;
EN1 = EN2 = 0 V
DC signal: VI = VCCI (Devices with suffix F) , VI = 0 V(Devices without suffix F) 2 2.9
ICC1 DC signal DC signal: VI = 0 V (Devices with suffix F) , VI = VCCI (Devices without suffix F) 1.4 2.3
ICC2 DC signal DC signal: VI = 0 V (Devices with suffix F) , VI = VCCI (Devices without suffix F) 1.7 2.6
ICC1 DC signal DC signal: VI = VCCI (Devices with suffix F) , VI = 0 V(Devices without suffix F) 3.8 5.6
ICC2 DC signal DC signal: VI = VCCI (Devices with suffix F) , VI = 0 V(Devices without suffix F) 3 4.3
ICC1 1 Mbps AC signal: All channels switching with square wave clock input;
CL = 15 pF
2.6 4
ICC2 1 Mbps 2.4 3.6
ICC1 10 Mbps 3.2 4.5
ICC2 10 Mbps 3.4 4.6
ICC1 100 Mbps 8.7 10.5
ICC2 100 Mbps 13.2 15.8
(1) VCCI = Input-side VCC; VCCO = Output-side VCC.

6.7 Electrical Characteristics, 3.3 V

VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = –2 mA; see Figure 7 VCCO(1) – 0.4 VCCO(1) – 0.2 V
VOL Low-level output voltage IOL = 2 mA; see Figure 7 0.2 0.4 V
VI(HYS) Input threshold voltage hysteresis 0.1 × VCCO(1) V
IIH High-level input current VIH = VCCI(1) at INx or ENx 10 μA
IIL Low-level input current VIL = 0 V at INx or ENx -10 μA
CMTI Common-mode transient immunity VI = VCCI(1) or 0 V; see Figure 10 70 100 kV/μs
ICC1 Supply current Disable;
EN1 = EN2 = 0 V
DC signal: VI = 0 V (Devices with suffix F) , VI = VCCI (Devices without suffix F) 1.0 1.6 mA
ICC2 Disable;
EN1 = EN2 = 0 V
DC signal: VI = 0 V (Devices with suffix F) , VI = VCCI (Devices without suffix F) 0.8 1.3
ICC1 Disable;
EN1 = EN2 = 0 V
DC signal: VI = VCCI (Devices with suffix F) , VI = 0 V(Devices without suffix F) 3.3 4.8
ICC2 Disable;
EN1 = EN2 = 0 V
DC signal: VI = VCCI (Devices with suffix F) , VI = 0 V(Devices without suffix F) 1.9 2.9
ICC1 DC signal DC signal: VI = 0 V (Devices with suffix F) , VI = VCCI (Devices without suffix F) 1.4 2.3
ICC2 DC signal DC signal: VI = 0 V (Devices with suffix F) , VI = VCCI (Devices without suffix F) 1.7 2.6
ICC1 DC signal DC signal: VI = VCCI (Devices with suffix F) , VI = 0 V(Devices without suffix F) 3.8 5.6
ICC2 DC signal DC signal: VI = VCCI (Devices with suffix F) , VI = 0 V(Devices without suffix F) 2.9 4.3
ICC1 1 Mbps AC signal: All channels switching with square wave clock input;
CL = 15 pF
2.6 4
ICC2 1 Mbps 2.4 3.5
ICC1 10 Mbps 3.0 4.3
ICC2 10 Mbps 3.1 4.3
ICC1 100 Mbps 6.9 8.3
ICC2 100 Mbps 10.1 12.2
(1) VCCI = Input-side VCC; VCCO = Output-side VCC.

6.8 Electrical Characteristics, 2.5 V

VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = –1 mA; see Figure 7 VCCO(1) – 0.4 VCCO(1) – 0.2 V
VOL Low-level output voltage IOL = 1 mA; see Figure 7 0.2 0.4 V
VI(HYS) Input threshold voltage hysteresis 0.1 × VCCO(1) V
IIH High-level input current VIH = VCCI(1) at INx or ENx 10 μA
IIL Low-level input current VIL = 0 V at INx or ENx –10 μA
CMTI Common-mode transient immunity VI = VCCI(1) or 0 V; see Figure 10 70 100 kV/μs
ICC1 Supply current Disable;
EN1 = EN2 = 0 V
DC signal: VI = 0 V (Devices with suffix F) , VI = VCCI (Devices without suffix F) 0.9 1.6 mA
ICC2 Disable;
EN1 = EN2 = 0 V
DC signal: VI = 0 V (Devices with suffix F) , VI = VCCI (Devices without suffix F) 0.8 1.3
ICC1 Disable;
EN1 = EN2 = 0 V
DC signal: VI = VCCI (Devices with suffix F) , VI = 0 V(Devices without suffix F) 3.3 4.8
ICC2 Disable;
EN1 = EN2 = 0 V
DC signal: VI = VCCI (Devices with suffix F) , VI = 0 V(Devices without suffix F) 1.9 2.9
ICC1 DC signal DC signal: VI = 0 V (Devices with suffix F) , VI = VCCI (Devices without suffix F) 1.4 2.3
ICC2 DC signal DC signal: VI = 0 V (Devices with suffix F) , VI = VCCI (Devices without suffix F) 1.7 2.6
ICC1 DC signal DC signal: VI = VCCI (Devices with suffix F) , VI = 0 V(Devices without suffix F) 3.8 5.6
ICC2 DC signal DC signal: VI = VCCI (Devices with suffix F) , VI = 0 V(Devices without suffix F) 2.9 4.3
ICC1 1 Mbps AC signal: All channels switching with square wave clock input;
CL = 15 pF
2.6 4
ICC2 1 Mbps 2.3 3.5
ICC1 10 Mbps 2.9 4.3
ICC2 10 Mbps 2.9 4.1
ICC1 100 Mbps 5.8 7.2
ICC2 100 Mbps 8.2 10.0
(1) VCCI = Input-side VCC; VCCO = Output-side VCC.

6.9 Switching Characteristics, 5 V

VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time See Figure 7 6 11 16 ns
PWD(1) Pulse width distortion |tPHL – tPLH| 0.55 4.1
tsk(o) (2) Channel-to-channel output skew time Same-direction channels 2.5
tsk(pp) (3) Part-to-part skew time 4.5
tr Output signal rise time See Figure 7 1.7 3.9
tf Output signal fall time 1.9 3.9
tPHZ Disable propagation delay, high-to-high impedance output See Figure 8 12 20
tPLZ Disable propagation delay, low-to-high impedance output 12 20
tPZH Enable propagation delay, high impedance-to-high output 10 20 ns
Enable propagation delay, high impedance-to-high output 2 2.5 μs
tPZL Enable propagation delay, high impedance-to-low output 2 2.5 μs
Enable propagation delay, high impedance-to-low output 10 20 ns
tfs Default output delay time from input power loss Measured from the time VCC goes below 1.7 V. See Figure 9 0.2 9 μs
tie Time interval error 216 – 1 PRBS data at 100 Mbps 0.90 ns
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads.

6.10 Switching Characteristics, 3.3 V

VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time See Figure 7 6 10.8 16 ns
PWD(1) Pulse width distortion |tPHL – tPLH| 0.7 4.2
tsk(o) (2) Channel-to-channel output skew time Same-direction channels 2.2
tsk(pp) (3) Part-to-part skew time 4.5
tr Output signal rise time See Figure 7 0.8 3
tf Output signal fall time 0.8 3
tPHZ Disable propagation delay, high-to-high impedance output See Figure 8 17 32
tPLZ Disable propagation delay, low-to-high impedance output 17 32
tPZH Enable propagation delay, high impedance-to-high output 17 32 ns
Enable propagation delay, high impedance-to-high output 2 2.5 μs
tPZL Enable propagation delay, high impedance-to-low output 2 2.5 μs
Enable propagation delay, high impedance-to-low output 17 32 ns
tfs Default output delay time from input power loss Measured from the time VCC goes below 1.7 V. See Figure 9 0.2 9 μs
tie Time interval error 216 – 1 PRBS data at 100 Mbps 0.91 ns
(1) Also known as Pulse Skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads.

6.11 Switching Characteristics, 2.5 V

VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time See Figure 7 7.5 11.7 17.5 ns
PWD(1) Pulse width distortion |tPHL – tPLH| 0.66 4.2
tsk(o) (2) Channel-to-channel output skew time Same-direction Channels 2.2
tsk(pp) (3) Part-to-part skew time 4.5
tr Output signal rise time See Figure 7 1 3.5
tf Output signal fall time 1.2 3.5
tPHZ Disable propagation delay, high-to-high impedance output See Figure 8 22 45
tPLZ Disable propagation delay, low-to-high impedance output 22 45
tPZH Enable propagation delay, high impedance-to-high output 18 45 ns
Enable propagation delay, high impedance-to-high output 2 2.5 μs
tPZL Enable propagation delay, high impedance-to-low output 2 2.5 μs
Enable propagation delay, high impedance-to-low output 18 45 ns
tfs Default output delay time from input power loss Measured from the time VCC goes below 1.7 V. See Figure 9 0.2 9 μs
tie Time interval error 216 – 1 PRBS data at 100 Mbps 0.91 ns
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads.

6.12 Typical Characteristics

ISO7831 ISO7831F D001_SLLSEP8.gif
TA = 25°C CL = 15 pF
Figure 1. Supply Current vs Data Rate (With 15-pF Load)
ISO7831 ISO7831F D003_SLLSEJ0.gif
TA = 25°C
Figure 3. High-Level Output Voltage vs High-level Output Current
ISO7831 ISO7831F D005_SLLSEJ0.gif
Figure 5. Power Supply Undervoltage Threshold vs Free-Air Temperature
ISO7831 ISO7831F D002_SLLSEP8.gif
TA = 25°C CL = No Load
Figure 2. Supply Current vs Data Rate (With No Load)
ISO7831 ISO7831F D004_SLLSEJ0.gif
TA = 25°C
Figure 4. Low-Level Output Voltage vs Low-Level Output Current
ISO7831 ISO7831F D006_SLLSEJ0.gif
Figure 6. Propagation Delay Time vs Free-Air Temperature