SLLS868T September   2007  – April 2017 ISO7240C , ISO7240CF , ISO7240M , ISO7241C , ISO7241M , ISO7242C , ISO7242M

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Pin Configurations and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety Limiting Values
    9. 7.9  Electrical Characteristics: VCC1 and VCC2 at 5-V Operation
    10. 7.10 Supply Current Characteristics: VCC1 and VCC2 at 5-V Operation
    11. 7.11 Electrical Characteristics: VCC1 at 5-V, VCC2 at 3.3-V Operation
    12. 7.12 Supply Current Characteristics: VCC1 at 5-V, VCC2 at 3.3-V Operation
    13. 7.13 Electrical Characteristics: VCC1 at 3.3-V, VCC2 at 5-V Operation
    14. 7.14 Supply Current Characteristics: VCC1 at 3.3-V, VCC2 at 5-V Operation
    15. 7.15 Electrical Characteristics: VCC1 and VCC2 at 3.3 V Operation
    16. 7.16 Supply Current Characteristics: VCC1 and VCC2 at 3.3 V Operation
    17. 7.17 Switching Characteristics: VCC1 and VCC2 at 5-V Operation
    18. 7.18 Switching Characteristics: VCC1 at 5-V, VCC2 at 3.3-V Operation
    19. 7.19 Switching Characteristics: VCC1 at 3.3-V and VCC2 at 5-V Operation
    20. 7.20 Switching Characteristics: VCC1 and VCC2 at 3.3-V Operation
    21. 7.21 Insulation Characteristics Curves
    22. 7.22 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device I/O Schematics
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Isolated Data Acquisition System for Process Control
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Isolated SPI for an Analog Input Module with 16 Inputs
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curve
      3. 10.2.3 Isolated RS-232 Interface
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 PCB Material
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Related Links
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8 Parameter Measurement Information

ISO7240CF ISO7240C ISO7240M ISO7241C ISO7241M ISO7242C ISO7242M swt_lls868.gif
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 11. Switching Characteristic Test Circuit and Voltage Waveforms
ISO7240CF ISO7240C ISO7240M ISO7241C ISO7241M ISO7242C ISO7242M tst_cir_wf_lls868.gif
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50Ω.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 12. Enable or Disable Propagation-Delay Time Test Circuit and Waveform
ISO7240CF ISO7240C ISO7240M ISO7241C ISO7241M ISO7242C ISO7242M failsafe_lls868.gif
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 13. Failsafe Delay Time Test Circuit and Voltage Waveforms
ISO7240CF ISO7240C ISO7240M ISO7241C ISO7241M ISO7242C ISO7242M wake_time_lls868.gif

NOTE:

The test that yields the longest time is used in this data sheet.
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50Ω.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 14. Wake Time From Input Disable Test Circuit and Voltage Waveforms
ISO7240CF ISO7240C ISO7240M ISO7241C ISO7241M ISO7242C ISO7242M com_tran_imm_test_circ_sllsei6.gif
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω.
Figure 15. Common-Mode Transient Immunity Test Circuit and Voltage Waveform
ISO7240CF ISO7240C ISO7240M ISO7241C ISO7241M ISO7242C ISO7242M p_t_p_eye_lls868.gif

NOTE:

PRBS bit pattern run length is 216 – 1. Transition time is 800 ps. NRZ data input has no more than five consecutive 1s or 0s.
Figure 16. Peak-to-Peak Eye-Pattern Jitter Test Circuit and Voltage Waveform