ZHCSNH7 May   2022 INA190-EP

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Precision Current Measurement
      2. 7.3.2 Low Input Bias Current
      3. 7.3.3 Low Quiescent Current With Output Enable
      4. 7.3.4 Bidirectional Current Monitoring
      5. 7.3.5 High-Side and Low-Side Current Sensing
      6. 7.3.6 High Common-Mode Rejection
      7. 7.3.7 Rail-to-Rail Output Swing
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Unidirectional Mode
      3. 7.4.3 Bidirectional Mode
      4. 7.4.4 Input Differential Overload
      5. 7.4.5 Shutdown
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Basic Connections
      2. 8.1.2 RSENSE and Device Gain Selection
      3. 8.1.3 Signal Conditioning
      4. 8.1.4 Common-Mode Voltage Transients
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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6.5 Electrical Characteristics

at TA = 25°C, VSENSE = VIN+ – VIN–, VS = 1.8 V to 5.0 V, VIN+ = 12 V, VREF = VS / 2, and VENABLE = VS (unless otherwise noted)
PARAMETER CONDITIONS MIN TYP MAX UNIT
INPUT
CMRR Common-mode rejection ratio  VSENSE = 0 mV, VIN+ = –0.1 V to 40 V, TA = –55°C to +150°C 132 150 dB
VOS Offset voltage, RTI(1) VS = 1.8 V, VSENSE = 0 mV –3 ±15 µV
dVOS/dT Offset drift, RTI VSENSE = 0 mV, TA = –55°C to +150°C ±10 ±80 nV/°C
PSRR Power-supply rejection ratio, RTI VSENSE = 0 mV, VS = 1.7 V to 5.5 V,  TA = –55°C to +150°C –1 ±7 µV/V
IIB Input bias current VSENSE = 0 mV ±0.5 ±3 nA
IIB Input bias current VSENSE = 0 mV,  TA = –55°C to +150°C ±20 nA
IIO Input offset current VSENSE = 0 mV ±0.07 ±3 nA
IIO Input offset current VSENSE = 0 mV, TA = –55°C to +150°C ±20 nA
OUTPUT
G Gain A1 devices 25 V/V
A2 devices 50
A3 devices 100
A4 devices 200
A5 devices 500
EG Gain error VOUT = 0.1 V to VS – 0.1 V A1 devices –0.04% ±0.2%
A2, A3, A4 devices –0.06% ±0.3%
A5 devices –0.08% ±0.4%
Gain error drift TA = –55°C to +150°C 2 7 ppm/°C
Nonlinearity error(2) VOUT = 0.1 V to VS – 0.1 V ±0.0025% ±0.025%
RVRR Reference voltage rejection ratio
VREF = 100 mV to VS – 100 mV,
TA = –55°C to +150°C		 A1 devices ±2 ±10 µV/V
A2 devices ±1 ±6
A3 devices ±0.5 ±4
A4, A5 devices ±0.25 ±3
Maximum capacitive load No sustained oscillation 1 nF
VOLTAGE OUTPUT
VSP Swing to VS power-supply rail VS = 1.8 V, RL = 10 kΩ to GND, TA = –55°C to +150°C (VS) – 20 (VS) – 40 mV
VSN Swing to GND VS = 1.8 V, RL = 10 kΩ to GND, TA = –55°C to +150°C,
VSENSE = –10 mV, VREF = 0 V		 (VGND) + 0.05 (VGND) + 1 mV
VZL Zero current output voltage VS = 1.8 V, RL = 10 kΩ to GND,
TA = –55°C to +150°C, VSENSE = 0 mV,
VREF = 0 V		 A1, A2, A3 devices (VGND) + 1 (VGND) + 3 mV
A4 devices (VGND) + 2 (VGND) + 4
A5 devices (VGND) + 3 (VGND) + 9
FREQUENCY RESPONSE
BW Bandwidth(2) A1 devices, CLOAD = 10 pF 20 45 87 kHz
A2 devices, CLOAD = 10 pF 18 37 78
A3 devices, CLOAD = 10 pF 16 35 73
A4 devices, CLOAD = 10 pF 14 33 64
A5 devices, CLOAD = 10 pF 9 27 44
SR Slew rate(2) VS = 5.0 V, VOUT = 0.5 V to 4.5 V 0.1 0.3 1 V/µs
tS Settling time(2) From current step to within 1% of final value 8 30 100 µs
NOISE, RTI(1)
Voltage noise density(2) 25 75 225 nV/√Hz
ENABLE
IEN Leakage input current 0 V ≤ VENABLE ≤ VS, TA = –55°C to +150°C 1 100 nA
VIH High-level input voltage TA = –55°C to +150°C 0.7 × VS 6 V
VIL Low-level input voltage TA = –55°C to +150°C 0 0.3 × VS V
VHYS Hysteresis 300 mV
IODIS Output leakage disabled VS = 5.0 V, VOUT = 0 V to 5.0 V, VENABLE = 0 V, TA = –55°C to +150°C 1 5 µA
POWER SUPPLY
IQ Quiescent current VS = 1.8 V, VSENSE = 0 mV 48 65 µA
VS = 1.8 V, VSENSE = 0 mV, TA = –55°C to +150°C 90
IQDIS Quiescent current disabled VENABLE = 0 V, VSENSE = 0 mV 10 100 nA
VENABLE = 0 V, VSENSE = 0 mV, TA = –55°C to +150°C 500
(1) RTI = referred-to-input.
(2) Specification based on statistical simulation results or characterization, not tested in final production.