ZHCSBS1A November   2013  – August 2015 HD3SS6126

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - Device Parameters
    6. 6.6 Electrical Characteristics - Signal Switch Parameters
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Power Supply
        2. 8.2.2.2 Differential Pairs
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11器件和文档支持
    1. 11.1 社区资源
    2. 11.2 商标
    3. 11.3 静电放电警告
    4. 11.4 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

10 Layout

10.1 Layout Guidelines

Generally, impedance match becomes critical in such high-speed signal applications to avoid reflection. Each differential-signal pair must have a differential impedance of about 90 Ω ±15% (for PCIe or DP, 100 Ω ±10%) with single-end signal impedance about 50 Ω to ground. Usually, Microstrip is used to accomplish impedance match. Four layers are recommended for a low-EMI PCB design. shows physical geometries of differential traces to form Microstrip. In order to better maintain signal integrity, reference the following:

  1. Route high-speed differential signals on the top layer with a solid ground layer under them to accomplish controlled impedance, while avoiding vias and stubs which may cause impedance discontinuities. If vias must be used, make sure the space of the vias is as minimal as possible.
  2. Be sure both the length of differential traces and the length of differential signal pairs are matched in order to reduce intrapair skew and interpair skew separately which also does good to low EMI. TI recommends keeping the space of the traces of the differential signal the same across the entire length of the trace to keep impedance match and reduce EMI.
  3. Route low-speed, but fast-edged control signals on the bottom layer to minimize the crosstalk of the high-speed signal.
  4. For other adjacent signal traces on the same layer, make distance L ≥ 3 S to facilitate impedance match.
  5. TI reccommends using 45° bends instead of 90° bends in order to maintain signal integrity and low EMI.

10.2 Layout Examples

HD3SS6126 PCB_Layers.gif Figure 10. PCB Layers Example
HD3SS6126 USB_routing_example.png Figure 11. USB Signals Routing Example