ZHCSKG1C November   2015  – October 2019 DS280BR810

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     简化电路原理图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Electrical Characteristics -- Serial Management Bus Interface
    7. 6.7 Timing Requirements -- Serial Management Bus Interface
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Data Path Operation
      2. 7.3.2 AC-Coupled Receiver and Transmitter
      3. 7.3.3 Signal Detect
      4. 7.3.4 2-Stage CTLE
      5. 7.3.5 Driver DC Gain Control
      6. 7.3.6 FIR Filter (Limiting Mode)
      7. 7.3.7 Configurable SMBus Address
    4. 7.4 Device Functional Modes
      1. 7.4.1 SMBus Slave Mode Configuration
      2. 7.4.2 SMBus Master Mode Configuration (EEPROM Self Load)
    5. 7.5 Programming
      1. 7.5.1 Transfer of Data with the SMBus Interface
    6. 7.6 Register Maps
      1. 7.6.1 Register Types: Global, Shared, and Channel
      2. 7.6.2 Global Registers: Channel Selection and ID Information
        1. Table 2. Global Register Map
      3. 7.6.3 Shared Registers
        1. Table 3. Shared Register Map
      4. 7.6.4 Channel Registers
        1. Table 4. Channel Register Map
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Backplane and Mid-Plane Reach Extension
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
      2. 8.2.2 Front-Port Applications
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Initialization Set Up
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information
      2. 12.1.2 Tape and Reel Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.6.3 Shared Registers

Table 3. Shared Register Map

Addr [HEX] Bit Default [HEX] Mode EEPROM Field Description
0x00 0x0C General
7 0 R N I2C_ADDR[3] I2C strap observation. The device 7-bit slave address is 0x18 + I2C_ADDR[3:0].
6 0 R N I2C_ADDR[2]
5 0 R N I2C_ADDR[1]
4 0 R N I2C_ADDR[0]
3 0 R N RESERVED RESERVED
2 0 R N RESERVED RESERVED
1 0 R N RESERVED RESERVED
0 0 R N RESERVED RESERVED
0x01 0x00 Version Revision
7 0 R N RESERVED RESERVED
6 0 R N RESERVED RESERVED
5 0 R N RESERVED RESERVED
4 0 R N RESERVED RESERVED
3 0 R N RESERVED RESERVED
2 0 R N RESERVED RESERVED
1 0 R N RESERVED RESERVED
0 0 R N RESERVED RESERVED
0x02 0x00 Channel Control
7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
0x03 0x00 Channel Control
7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
0x04 0x01 General
7 0 RW N RESERVED RESERVED
6 0 RWSC N RST_I2C_REGS 1: Reset shared registers, bit is self-clearing.
0: Normal operation
5 0 RWSC N RST_I2C_MAS 1: Self-clearing reset for I2C master.
0: Normal operation
4 0 RW N FRC_EEPRM_RD 1: Override EN_SMB and input chain status to force EEPROM Configuration.
0: Normal operation
3 0 RW N RESERVED RESERVED
2 0 RW N REGS_CLOCK_EN RESERVED
1 0 RW N I2C_MAS_CLK_EN RESERVED
0 1 RW N I2CSLV_CLK_EN RESERVED
0x05 0x00 General
7 0 RW N DISAB_EEPRM_CFG 1: Disable Master Mode EEPROM Configuration (If not started, not effective midway or after configuration).
0: Normal operation
6 0 RW N CRC_EN RESERVED
5 0 RW N ML_TEST
_CONTROL		 RESERVED
4 0 R N EEPROM_READING
_DONE		 Sets 1 when EEPROM reading done.
3 0 R N RESERVED RESERVED
2 0 R Y CAL_CLK_INV_DIS 1: Disable the inversion of CAL_CLK_OUT.
0: Normal operation, CAL_CLK_OUT is inverted with respect to CAL_CLK_IN.
1 0 R N RESERVED RESERVED
0 0 R N TEST0_AS_CAL
_CLK		 RESERVED
0x06 0x00 General
7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
0x07 0x00 General
7 0 RW N RESERVED RESERVED
6 0 R N CAL_CLK_DET 1: Indicates that CAL_CLK has been detected.
0: Indicates that CAL_CLK has not been detected.
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N MR_CAL_CLK_DET
_DIS		 1: Disable CAL_CLK detect.
0: Enable CAL_CLK detect.
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW Y DIS_CAL_CLK_OUT 1: Disable CAL_CLK_OUT, output is high-Z.
0: Enable CAL_CLK_OUT.
0x08 0x00 General
7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
0x09 0x00 General
7 0 R N RESERVED RESERVED
6 0 R N RESERVED RESERVED
5 0 R N RESERVED RESERVED
4 0 R N RESERVED RESERVED
3 0 R N RESERVED RESERVED
2 0 R N RESERVED RESERVED
1 0 R N RESERVED RESERVED
0 0 R N RESERVED RESERVED
0x0A 0x00 General
7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 R N RESERVED RESERVED
0 0 R N RESERVED RESERVED
0x0B 0x00
7 0 R N EECFG_CMPLT 11: Not valid.
10: EEPROM load completed successfully.
6 0 R N EECFG_FAIL 01: EEPROM load failed after 64 attempts.
00: EEPROM load in progress.
5 0 R N EECFG_ATMPT[5] Indicates number of attempts made to load EEPROM image.
4 0 R N EECFG_ATMPT[4]
3 0 R N EECFG_ATMPT[3]
2 0 R N EECFG_ATMPT[2]
1 0 R N EECFG_ATMPT[1]
0 0 R N EECFG_ATMPT[0]
0x0C 0x91
7 1 RW N I2C_FAST 1: EEPROM load uses Fast I2C Mode (400 kHz).
0: EEPROM load uses Standard I2C Mode (100 kHz).
6 0 RW N I2C_SDA_HOLD[2] Internal SDA Hold Time
This field configures the amount of internal hold time provided for the SDA input relative to the SDC input. Units are 100 ns.
5 0 RW N I2C_ SDA_HOLD[1]
4 1 RW N I2C_ SDA_HOLD[0]
3 0 RW N I2C_FLTR_DEPTH[3] I2C Glitch Filter Depth
This field configures the maximum width of glitch pulses on the SDC and SDA inputs that will be rejected. Units are 100 ns.
2 0 RW N I2C_FLTR_DEPTH[2]
1 0 RW N I2C_FLTR_DEPTH[1]
0 1 RW N I2C_FLTR_DEPTH[0]