ZHCSRO2 February   2023 DS160PR1601

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD and Latchup Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Charateristics
    8. 6.8 Typical Characteristics
    9. 6.9 Typical Jitter Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Control and Configuration Interface
      1. 7.3.1 Pin Configurations for Lanes
        1. 7.3.1.1 Five-Level Control Inputs
      2. 7.3.2 SMBUS/I2C Register Control Interface
      3. 7.3.3 SMBus/I 2 C Primary Mode Configuration (EEPROM Self Load)
    4. 7.4 Feature Description
      1. 7.4.1 Linear Equalization
      2. 7.4.2 Flat-Gain
      3. 7.4.3 Analog EyeScan
      4. 7.4.4 Receiver Detect State Machine
      5. 7.4.5 Integrated Capacitors
    5. 7.5 Device Functional Modes
      1. 7.5.1 Active PCIe Mode
      2. 7.5.2 Active Buffer Mode
      3. 7.5.3 Standby Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 PCIe x16 Lane Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  10. 10Mechanical, Packaging, and Orderable Information

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6.5 DC Electrical Characteristics

over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power
PACT Device active power  32-channels (16-lanes), EQ = 0-3  4.7 6.0 W
PACT Device active power  32-channels (16-lanes), EQ = 4-19  5.8 7.0 W
PRXDET Device power consumption while waiting for far end receiver terminations All channels enabled but no far end receiver detected 660 mW
PSTBY Device power consumption in standby power mode All channels disabled 92 mW
Control IO
VOH High level output voltage Rpull-up = 4.7 kΩ (SDA, SCL, ALL_DONE_N pins) 2.1 V
VOL Low level output voltage IOL = –4 mA (SDA, SCL, ALL_DONE_N pins) 0.4 V
IIH Input high leakage current VInput = VCC, (SCL, SDA, PD, READ_EN_N pins) 40 µA
IIL Input low leakage current VInput = 0 V, (SCL, SDA, PD, READ_EN_N pins) -40 µA
IIH,FS Input high leakage current for fail safe input pins VInput = 3.6 V, VCC = 0 V, (SCL, SDA, PD, READ_EN_N pins) 800 µA
CIN-CTRL Input capacitance SDA, SCL, PD, READ_EN_Npins 1.2 pF
5 Level IOs (MODE, A/B_ADDR pins)
IIH_5L Input high leakage current, 4 level IOs VIN = 2.5 V 40 µA
IIL_5L Input low leakage current for all 4 level IOs except MODE. VIN = GND -40 µA
IIL_5L,MODE Input low leakage current for MODE pin VIN = GND -800 µA
Receiver
VRX-DC-CM RX DC Common Mode Voltage Device is in active or standby state 1.4 V
ZRX-DC Rx DC Single-Ended Impedance 50 Ω
ZRX-HIGH-IMP-DC-POS DC input CM input impedance during Reset or power-down Inputs are at VRX-DC-CM voltage 15 kΩ
Transmitter
ZTX-DIFF-DC DC Differential Tx Impedance Impedance of Tx during active signaling, VID,diff = 1Vpp 100 Ω
VTX-DC-CM Tx DC common mode Voltage 1.0 V
ITX-SHORT Tx Short Circuit Current Total current the Tx can supply when shorted to GND 70 mA