ZHCSDP9D October   2011  – April 2015 DS110DF410

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 典型应用图
  5. 5 修订历史记录
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device Data Path Operation
      2. 8.3.2 Signal Detect
      3. 8.3.3 CTLE
      4. 8.3.4 DFE
      5. 8.3.5 Clock and Data Recovery
      6. 8.3.6 Output Driver
      7. 8.3.7 Device Configuration
        1. 8.3.7.1 Rate and Subrate Setting
    4. 8.4 Device Functional Modes
      1. 8.4.1 SMBus Master Mode and SMBus Slave Mode
      2. 8.4.2 Address Lines <ADDR_[3:0]>
      3. 8.4.3 SDA and SDC
      4. 8.4.4 Standards-Based Modes
        1. 8.4.4.1 Ref_mode 3 Mode (Reference Clock Required)
        2. 8.4.4.2 False Lock Detector Setting
        3. 8.4.4.3 Reference Clock In
        4. 8.4.4.4 Reference Clock Out
        5. 8.4.4.5 Driver Output Voltage
        6. 8.4.4.6 Driver Output De-Emphasis
        7. 8.4.4.7 Driver Output Rise/Fall Time
        8. 8.4.4.8 INT
        9. 8.4.4.9 LOCK_3, LOCK_2, LOCK_1, and LOCK_0
    5. 8.5 Programming
      1. 8.5.1  SMBus Strap Observation
      2. 8.5.2  Device Revision and Device ID
      3. 8.5.3  Control/Shared Register Reset
      4. 8.5.4  Interrupt Channel Flag Bits
      5. 8.5.5  SMBus Master Mode Control Bits
      6. 8.5.6  Resetting Individual Channels of the Retimer
      7. 8.5.7  Interrupt Status
      8. 8.5.8  Overriding the CTLE Boost Setting
      9. 8.5.9  Overriding the VCO Search Values
      10. 8.5.10 Overriding the Output Multiplexer
      11. 8.5.11 Overriding the VCO Divider Selection
      12. 8.5.12 Using the PRBS Generator
      13. 8.5.13 Using the Internal Eye Opening Monitor
      14. 8.5.14 Overriding the DFE Tap Weights and Polarities
      15. 8.5.15 Enabling Slow Rise/Fall Time on the Output Driver
      16. 8.5.16 Inverting the Output Polarity
      17. 8.5.17 Overriding the Figure of Merit for Adaptation
      18. 8.5.18 Setting the Rate and Subrate for Lock Acquisition
      19. 8.5.19 Setting the Adaptation/Lock Mode
      20. 8.5.20 Initiating Adaptation
      21. 8.5.21 Setting the Reference Enable Mode
      22. 8.5.22 Overriding the CTLE Settings Used for CTLE Adaptation
      23. 8.5.23 Setting the Output Differential Voltage
      24. 8.5.24 Setting the Output De-Emphasis Setting
    6. 8.6 Register Maps
      1. 8.6.1 Register Information
      2. 8.6.2 Bit Fields in the Register Set
      3. 8.6.3 Writing to and Reading from the Control/Shared Registers
      4. 8.6.4 Channel Select Register
      5. 8.6.5 Reading to and Writing from the Channel Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 第三方产品免责声明
    2. 12.2 文档支持
      1. 12.2.1 相关文档
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 术语表
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

12 器件和文档支持

12.1 器件支持

12.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类产品或服务单独或与任何 TI 产品或服务一起的表示或认可。

12.2 文档支持

12.2.1 相关文档

相关文档，请参见《焊接相关的最大绝对额定值》，SNOA549。

有关 SMBus 规范及其操作说明，请参见 smbus.org/specs/。

12.3 商标

All trademarks are the property of their respective owners.

12.4 静电放电警告

esds-image

这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损伤。

12.5 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、首字母缩略词和定义。