SNLS396D January   2012  – January 2016 DS100MB203

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Electrical Characteristics - Serial Management Bus Interface
    7. 6.7 Timing Requirements - Serial Bus Interface
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 4-Level Input Configuration Guidelines
    4. 7.4 Device Functional Modes
      1. 7.4.1 Pin Control Mode
      2. 7.4.2 SMBUS Mode
    5. 7.5 Programming
      1. 7.5.1 SMBUS Master Mode
    6. 7.6 Register Maps
      1. 7.6.1 System Management Bus (SMBus) and Configuration Registers
        1. 7.6.1.1 Transfer of Data Through the SMBus
        2. 7.6.1.2 SMBus Transactions
        3. 7.6.1.3 Writing a Register
        4. 7.6.1.4 Reading a Register
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 General Recommendations
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
    1. 9.1 Power Supply Bypassing
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

8 Application and Implementation

8.1 Application Information

8.1.1 General Recommendations

The DS100MB203 is a high-performance circuit capable of delivering excellent performance. Pay careful attention to the details associated with high-speed design as well as providing a clean power supply. Refer to the information below and Revision 4 of the LVDS Owner's Manual for more detailed information on high speed design tips to address signal integrity design issues.

DS100MB203 TL1.gif Figure 8. Test Set-Up Connections Diagram
DS100MB203 TL1TL2.gif Figure 9. Test Set-Up Connections Diagram

8.2 Typical Application

DS100MB203 MBapplication.gif Figure 10. Storage Application

8.2.1 Design Requirements

As with any high-speed design, there are many factors which influence the overall performance. Below are a list of critical areas for consideration and study during design.

  • Use 100-Ω impedance traces. Generally these are very loosely coupled to ease routing length differences.
  • Place AC-coupling capacitors near to the receiver end of each channel segment to minimize reflections.
  • The maximum body size for AC-coupling capacitors is 0402.
  • Back-drill connector vias and signal vias to minimize stub length.
  • Use Reference plane vias to ensure a low inductance path for the return current.

8.2.2 Detailed Design Procedure

The DS100MB203 is designed to be placed at an offset location with respect to the overall channel attenuation. In order to optimize performance, the repeater requires tuning to extend the reach of the cable or trace length while also recovering a solid eye opening. To tune the mux-buffer, the settings mentioned in Table 2 and Table 3 are recommended as a default starting point for most applications. Once these settings are configured, additional tuning of the EQ and, to a lesser extent, VOD may be required to optimize the repeater performance for each specific application environment.

Examples of the repeater performance as a generic high-speed datapath repeater are shown in the performance curves in the Application Curves section.

8.2.3 Application Curves

DS100MB203 30185459.png Figure 11. TL = 10-inch 5-mil FR4 Trace, 8 Gbps
MB203 Settings: EQ[1:0] = 0, F = 02'h, DEM[1:0] = 0, 1
DS100MB203 30185467.png Figure 13. TL = 30-inch 5-mil FR4 Trace, 8 Gbps
MB203 Settings: EQ[1:0] = R, 0 = 07'h, DEM[1:0] = 0, 1
DS100MB203 30185461.png Figure 12. TL = 20-inch 5–mil FR4 Trace, 8 Gbps
MB203 Settings: EQ[1:0] = 0, 1 = 03'h, DEM[1:0] = 0, 1
DS100MB203 30185463.png Figure 14. TL1 = 20-inch 5–mil FR4 Trace, TL2 = 10-inch 5–mil FR4 trace, 8 Gbps
MB203 Settings: EQ[1:0] = R, 1 = 03'h, DEM[1:0] = R, 0