ZHCSRX1E may   2010  – march 2023 DRV8840

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 PWM Motor Driver
      2. 7.3.2 Bridge Control
      3. 7.3.3 Current Regulation
      4. 7.3.4 Decay Mode and Braking
      5. 7.3.5 Blanking Time
      6. 7.3.6 Protection Circuits
        1. 7.3.6.1 Overcurrent Protection (OCP)
        2. 7.3.6.2 Thermal Shutdown (TSD)
        3. 7.3.6.3 Undervoltage Lockout (UVLO)
    4. 7.4 Device Functional Modes
      1. 7.4.1 nRESET and nSLEEP Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Current Regulation
        2. 8.2.2.2 Sense Resistor
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance Sizing
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Power Dissipation
      2. 10.3.2 Heatsinking
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
  12. 12Mechanical, Packaging, and Orderable Information

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5 Pin Configuration and Functions

GUID-00CC10F1-6F62-47A3-AF4F-950F73E7102F-low.gif Figure 5-1 PWP Package28-Pin HTSSOPTop View
Table 5-1 Pin Functions
PIN I/O(1) DESCRIPTION EXTERNAL COMPONENTS
OR CONNECTIONS
NAME NO.
POWER AND GROUND
GND 14, 28 — Device ground
VM 4, 11 — Bridge A power supply Connect to motor supply (8.2 - 45 V). Both pins must be connected to same supply.
V3P3OUT 15 O 3.3-V regulator output Bypass to GND with a 0.47-μF, 6.3-V ceramic capacitor. Can be used to supply VREF.
CP1 1 IO Charge pump flying capacitor Connect a 0.01-μF 50-V capacitor between CP1 and CP2.
CP2 2 IO Charge pump flying capacitor
VCP 3 IO High-side gate drive voltage Connect a 0.1-μF 16-V ceramic capacitor and a 1-MΩ resistor to VM.
CONTROL
PHASE 20 I Bridge phase (direction) Logic high sets OUT1 high, OUT2 low. Internal pulldown.
ENBL 21 I Bridge enable Logic high to enable H-bridge. Internal pulldown.
I0 23 I Current set inputs Sets winding current as a percentage of full-scale. Internal pulldown.
I1 24 I
I2 25 I
I3 26 I
I4 27 I
DECAY 19 I Decay (brake) mode Low = brake (slow decay), high = coast (fast decay). Internal pulldown and pullup.
nRESET 16 I Reset input Active-low reset input initializes the logic and disables the H-bridge outputs. Internal pulldown.
nSLEEP 17 I Sleep mode input Logic high to enable device, logic low to enter low-power sleep mode. Internal pulldown.
VREF 12,13 I Current set reference input Reference voltage for winding current set. Both pins must be connected together on the PCB.
STATUS
nFAULT 18 OD Fault Logic low when in fault condition (overtemperature, overcurrent)
OUTPUT
ISEN 6, 9 IO Bridge ground / Isense Connect to current sense resistor. Both pins must be connected together on the PCB.
OUT1 5, 10 O Bridge output 1 Connect to motor winding. Both pins must be connected together on the PCB.
OUT2 7, 8 O Bridge output 2 Connect to motor winding. Both pins must be connected together on the PCB.
(1) Directions: I = input, O = output, OZ = tri-state output, OD = open-drain output, IO = input/output