ZHCSJ46F December   2016  – December 2018 DRA74P , DRA75P

ADVANCE INFORMATION for pre-production products; subject to change without notice.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能方框图
  2. 2修订历史记录
  3. 3Device Comparison
    1. 3.1 Device Comparison Table
    2. 3.2 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  VIP
      2. 4.3.2  DSS
      3. 4.3.3  HDMI
      4. 4.3.4  EMIF
      5. 4.3.5  GPMC
      6. 4.3.6  Timers
      7. 4.3.7  I2C
      8. 4.3.8  HDQ1W
      9. 4.3.9  UART
      10. 4.3.10 McSPI
      11. 4.3.11 QSPI
      12. 4.3.12 McASP
      13. 4.3.13 USB
      14. 4.3.14 SATA
      15. 4.3.15 PCIe
      16. 4.3.16 DCAN and MCAN
      17. 4.3.17 GMAC_SW
      18. 4.3.18 MLB
      19. 4.3.19 eMMC/SD/SDIO
      20. 4.3.20 GPIO
      21. 4.3.21 KBD
      22. 4.3.22 PWM
      23. 4.3.23 ATL
      24. 4.3.24 Test Interfaces
      25. 4.3.25 System and Miscellaneous
        1. 4.3.25.1 Sysboot
        2. 4.3.25.2 PRCM
        3. 4.3.25.3 RTC
        4. 4.3.25.4 SDMA
        5. 4.3.25.5 INTC
        6. 4.3.25.6 Observability
        7. 4.3.25.7 Power Supplies
    4. 4.4 Pin Multiplexing
    5. 4.5 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH)
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Operating Performance Points
      1. 5.5.1 AVS and ABB Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6  Power Consumption Summary
    7. 5.7  Electrical Characteristics
      1. Table 5-6  LVCMOS DDR DC Electrical Characteristics
      2. Table 5-7  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      3. Table 5-8  IQ1833 Buffers DC Electrical Characteristics
      4. Table 5-9  IHHV1833 Buffers DC Electrical Characteristics
      5. Table 5-10 LVCMOS OSC Buffers DC Electrical Characteristics
      6. Table 5-11 BMLB18 Buffers DC Electrical Characteristics
      7. Table 5-12 BC1833IHHV Buffers DC Electrical Characteristics
      8. Table 5-13 Dual Voltage SDIO1833 DC Electrical Characteristics
      9. Table 5-14 Dual Voltage LVCMOS DC Electrical Characteristics
      10. 5.7.1      HDMIPHY DC Electrical Characteristics
      11. 5.7.2      USBPHY DC Electrical Characteristics
      12. 5.7.3      SATAPHY DC Electrical Characteristics
      13. 5.7.4      PCIEPHY DC Electrical Characteristics
    8. 5.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. Table 5-15 Recommended Operating Conditions for OTP eFuse Programming
      2. 5.8.1      Hardware Requirements
      3. 5.8.2      Programming Sequence
      4. 5.8.3      Impact to Your Hardware Warranty
    9. 5.9  Thermal Resistance Characteristics
      1. 5.9.1 Package Thermal Characteristics
    10. 5.10 Timing Requirements and Switching Characteristics
      1. 5.10.1 Timing Parameters and Information
        1. 5.10.1.1 Parameter Information
          1. 5.10.1.1.1 1.8V and 3.3V Signal Transition Levels
          2. 5.10.1.1.2 1.8V and 3.3V Signal Transition Rates
          3. 5.10.1.1.3 Timing Parameters and Board Routing Analysis
      2. 5.10.2 Interface Clock Specifications
        1. 5.10.2.1 Interface Clock Terminology
        2. 5.10.2.2 Interface Clock Frequency
      3. 5.10.3 Power Supply Sequences
      4. 5.10.4 Clock Specifications
        1. 5.10.4.1 Input Clocks / Oscillators
          1. 5.10.4.1.1 OSC0 External Crystal
          2. 5.10.4.1.2 OSC0 Input Clock
          3. 5.10.4.1.3 Auxiliary Oscillator OSC1 Input Clock
            1. 5.10.4.1.3.1 OSC1 External Crystal
            2. 5.10.4.1.3.2 OSC1 Input Clock
          4. 5.10.4.1.4 RTC Oscillator Input Clock
            1. 5.10.4.1.4.1 RTC Oscillator External Crystal
            2. 5.10.4.1.4.2 RTC Oscillator Input Clock
        2. 5.10.4.2 RC On-die Oscillator Clock
        3. 5.10.4.3 Output Clocks
        4. 5.10.4.4 DPLLs, DLLs
          1. 5.10.4.4.1 DPLL Characteristics
          2. 5.10.4.4.2 DLL Characteristics
          3. 5.10.4.4.3 DPLL and DLL Noise Isolation
      5. 5.10.5 Recommended Clock and Control Signal Transition Behavior
      6. 5.10.6 Peripherals
        1. 5.10.6.1  Timing Test Conditions
        2. 5.10.6.2  Virtual and Manual I/O Timing Modes
        3. 5.10.6.3  VIP
        4. 5.10.6.4  DSS
        5. 5.10.6.5  HDMI
        6. 5.10.6.6  EMIF
        7. 5.10.6.7  GPMC
          1. 5.10.6.7.1 GPMC/NOR Flash Interface Synchronous Timing
          2. 5.10.6.7.2 GPMC/NOR Flash Interface Asynchronous Timing
          3. 5.10.6.7.3 GPMC/NAND Flash Interface Asynchronous Timing
        8. 5.10.6.8  Timers
        9. 5.10.6.9  I2C
          1. Table 5-64 Timing Requirements for I2C Input Timings
          2. Table 5-65 Timing Requirements for I2C HS-Mode (I2C3/4/5 Only)
          3. Table 5-66 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
        10. 5.10.6.10 HDQ1W
          1. 5.10.6.10.1 HDQ / 1-Wire — HDQ Mode
          2. 5.10.6.10.2 HDQ/1-Wire—1-Wire Mode
        11. 5.10.6.11 UART
          1. Table 5-71 Timing Requirements for UART
          2. Table 5-72 Switching Characteristics Over Recommended Operating Conditions for UART
        12. 5.10.6.12 McSPI
        13. 5.10.6.13 QSPI
        14. 5.10.6.14 McASP
          1. Table 5-79 Timing Requirements for McASP1
          2. Table 5-80 Timing Requirements for McASP2
          3. Table 5-81 Timing Requirements for McASP3/4/5/6/7/8
          4. Table 5-82 Switching Characteristics Over Recommended Operating Conditions for McASP1
          5. Table 5-83 Switching Characteristics Over Recommended Operating Conditions for McASP2
          6. Table 5-84 Switching Characteristics Over Recommended Operating Conditions for McASP3/4/5/6/7/8
        15. 5.10.6.15 USB
          1. 5.10.6.15.1 USB1 DRD PHY
          2. 5.10.6.15.2 USB2 PHY
          3. 5.10.6.15.3 USB3 and USB4 DRD ULPI—SDR—Slave Mode—12-pin Mode
        16. 5.10.6.16 SATA
        17. 5.10.6.17 PCIe
        18. 5.10.6.18 CAN
          1. 5.10.6.18.1 DCAN
          2. 5.10.6.18.2 MCAN-FD
          3. Table 5-99  Timing Requirements for CANx Receive
          4. Table 5-100 Switching Characteristics Over Recommended Operating Conditions for CANx Transmit
        19. 5.10.6.19 GMAC_SW
          1. 5.10.6.19.1 GMAC MII Timings
            1. Table 5-101 Timing Requirements for miin_rxclk - MII Operation
            2. Table 5-102 Timing Requirements for miin_txclk - MII Operation
            3. Table 5-103 Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
            4. Table 5-104 Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit 10/100 Mbits/s
          2. 5.10.6.19.2 GMAC MDIO Interface Timings
          3. 5.10.6.19.3 GMAC RMII Timings
            1. Table 5-109 Timing Requirements for GMAC REF_CLK - RMII Operation
            2. Table 5-110 Timing Requirements for GMAC RMIIn Receive
            3. Table 5-111 Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII Operation
            4. Table 5-112 Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit 10/100 Mbits/s
          4. 5.10.6.19.4 GMAC RGMII Timings
            1. Table 5-116 Timing Requirements for rgmiin_rxc - RGMIIn Operation
            2. Table 5-117 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
            3. Table 5-118 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
            4. Table 5-119 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
        20. 5.10.6.20 MLB
        21. 5.10.6.21 eMMC/SD/SDIO
          1. 5.10.6.21.1 MMC1—SD Card Interface
            1. 5.10.6.21.1.1 Default speed, 4-bit data, SDR, half-cycle
            2. 5.10.6.21.1.2 High speed, 4-bit data, SDR, half-cycle
            3. 5.10.6.21.1.3 SDR12, 4-bit data, half-cycle
            4. 5.10.6.21.1.4 SDR25, 4-bit data, half-cycle
            5. 5.10.6.21.1.5 UHS-I SDR50, 4-bit data, half-cycle
            6. 5.10.6.21.1.6 UHS-I SDR104, 4-bit data, half-cycle
            7. 5.10.6.21.1.7 UHS-I DDR50, 4-bit data
          2. 5.10.6.21.2 MMC2 — eMMC
            1. 5.10.6.21.2.1 Standard JC64 SDR, 8-bit data, half cycle
            2. 5.10.6.21.2.2 High-Speed JC64 SDR, 8-bit data, half cycle
            3. 5.10.6.21.2.3 High-Speed HS200 JC64 SDR, 8-bit data, half cycle
            4. 5.10.6.21.2.4 High-Speed JC64 DDR, 8-bit data
          3. 5.10.6.21.3 MMC3 and MMC4—SDIO/SD
            1. 5.10.6.21.3.1 MMC3 and MMC4, SD Default Speed
            2. 5.10.6.21.3.2 MMC3 and MMC4, SD High Speed
            3. 5.10.6.21.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
            4. 5.10.6.21.3.4 MMC3 and MMC4, SD SDR25 Mode
            5. 5.10.6.21.3.5 MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
        22. 5.10.6.22 GPIO
        23. 5.10.6.23 ATL
          1. 5.10.6.23.1 ATL Electrical Data/Timing
            1. Table 5-175 Switching Characteristics Over Recommended Operating Conditions for ATL_CLKOUTx
        24. 5.10.6.24 System and Miscellaneous Interfaces
      7. 5.10.7 Emulation and Debug Subsystem
        1. 5.10.7.1 JTAG
          1. 5.10.7.1.1 JTAG Electrical Data/Timing
            1. Table 5-176 Timing Requirements for IEEE 1149.1 JTAG
            2. Table 5-177 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
            3. Table 5-178 Timing Requirements for IEEE 1149.1 JTAG With RTCK
            4. Table 5-179 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
        2. 5.10.7.2 TPIU
          1. 5.10.7.2.1 TPIU PLL DDR Mode
  6. 6Detailed Description
    1. 6.1  Description
    2. 6.2  Functional Block Diagram
    3. 6.3  MPU
    4. 6.4  DSP Subsystem
    5. 6.5  ISS
    6. 6.6  IVA
    7. 6.7  EVE
    8. 6.8  IPU
    9. 6.9  VPE
    10. 6.10 GPU
    11. 6.11 ATL Overview
    12. 6.12 Memory Subsystem
      1. 6.12.1 EMIF
      2. 6.12.2 GPMC
      3. 6.12.3 ELM
      4. 6.12.4 OCMC
    13. 6.13 Interprocessor Communication
      1. 6.13.1 Mailbox
      2. 6.13.2 Spinlock
    14. 6.14 Interrupt Controller
    15. 6.15 EDMA
    16. 6.16 Peripherals
      1. 6.16.1  VIP
      2. 6.16.2  DSS
      3. 6.16.3  Timers
      4. 6.16.4  I2C
      5. 6.16.5  HDQ1W
      6. 6.16.6  UART
        1. 6.16.6.1 UART Features
        2. 6.16.6.2 IrDA Features
        3. 6.16.6.3 CIR Features
      7. 6.16.7  McSPI
      8. 6.16.8  QSPI
      9. 6.16.9  McASP
      10. 6.16.10 USB
      11. 6.16.11 SATA
      12. 6.16.12 PCIe
      13. 6.16.13 CAN
      14. 6.16.14 GMAC_SW
      15. 6.16.15 MLB
      16. 6.16.16 eMMC/SD/SDIO
      17. 6.16.17 GPIO
      18. 6.16.18 ePWM
      19. 6.16.19 eCAP
      20. 6.16.20 eQEP
    17. 6.17 On-Chip Debug
  7. 7Applications, Implementation, and Layout
    1. 7.1 Introduction
      1. 7.1.1 Initial Requirements and Guidelines
    2. 7.2 Power Optimizations
      1. 7.2.1 Step 1: PCB Stack-up
      2. 7.2.2 Step 2: Physical Placement
      3. 7.2.3 Step 3: Static Analysis
        1. 7.2.3.1 PDN Resistance and IR Drop
      4. 7.2.4 Step 4: Frequency Analysis
      5. 7.2.5 System ESD Generic Guidelines
        1. 7.2.5.1 System ESD Generic PCB Guideline
        2. 7.2.5.2 Miscellaneous EMC Guidelines to Mitigate ESD Immunity
      6. 7.2.6 EMI / EMC Issues Prevention
        1. 7.2.6.1 Signal Bandwidth
        2. 7.2.6.2 Signal Routing
          1. 7.2.6.2.1 Signal Routing—Sensitive Signals and Shielding
          2. 7.2.6.2.2 Signal Routing—Outer Layer Routing
        3. 7.2.6.3 Ground Guidelines
          1. 7.2.6.3.1 PCB Outer Layers
          2. 7.2.6.3.2 Metallic Frames
          3. 7.2.6.3.3 Connectors
          4. 7.2.6.3.4 Guard Ring on PCB Edges
          5. 7.2.6.3.5 Analog and Digital Ground
    3. 7.3 Core Power Domains
      1. 7.3.1 General Constraints and Theory
      2. 7.3.2 Voltage Decoupling
      3. 7.3.3 Static PDN Analysis
      4. 7.3.4 Dynamic PDN Analysis
      5. 7.3.5 Power Supply Mapping
      6. 7.3.6 DPLL Voltage Requirement
      7. 7.3.7 Loss of Input Power Event
      8. 7.3.8 Example PCB Design
        1. 7.3.8.1 Example Stack-up
        2. 7.3.8.2 vdd_mpu Example Analysis
    4. 7.4 Single-Ended Interfaces
      1. 7.4.1 General Routing Guidelines
      2. 7.4.2 QSPI Board Design and Layout Guidelines
    5. 7.5 Differential Interfaces
      1. 7.5.1 General Routing Guidelines
      2. 7.5.2 USB 2.0 Board Design and Layout Guidelines
        1. 7.5.2.1 Background
        2. 7.5.2.2 USB PHY Layout Guide
          1. 7.5.2.2.1 General Routing and Placement
          2. 7.5.2.2.2 Specific Guidelines for USB PHY Layout
            1. 7.5.2.2.2.1  Analog, PLL, and Digital Power Supply Filtering
            2. 7.5.2.2.2.2  Analog, Digital, and PLL Partitioning
            3. 7.5.2.2.2.3  Board Stackup
            4. 7.5.2.2.2.4  Cable Connector Socket
            5. 7.5.2.2.2.5  Clock Routings
            6. 7.5.2.2.2.6  Crystals/Oscillator
            7. 7.5.2.2.2.7  DP/DM Trace
            8. 7.5.2.2.2.8  DP/DM Vias
            9. 7.5.2.2.2.9  Image Planes
            10. 7.5.2.2.2.10 JTAG Interface
            11. 7.5.2.2.2.11 Power Regulators
        3. 7.5.2.3 Electrostatic Discharge (ESD)
          1. 7.5.2.3.1 IEC ESD Stressing Test
            1. 7.5.2.3.1.1 Test Mode
            2. 7.5.2.3.1.2 Air Discharge Mode
            3. 7.5.2.3.1.3 Test Type
          2. 7.5.2.3.2 TI Component Level IEC ESD Test
          3. 7.5.2.3.3 Construction of a Custom USB Connector
          4. 7.5.2.3.4 ESD Protection System Design Consideration
        4. 7.5.2.4 References
      3. 7.5.3 USB 3.0 Board Design and Layout Guidelines
        1. 7.5.3.1 USB 3.0 interface introduction
        2. 7.5.3.2 USB 3.0 General routing rules
      4. 7.5.4 HDMI Board Design and Layout Guidelines
        1. 7.5.4.1 HDMI Interface Schematic
        2. 7.5.4.2 TMDS General Routing Guidelines
        3. 7.5.4.3 TPD5S115
        4. 7.5.4.4 HDMI ESD Protection Device (Required)
        5. 7.5.4.5 PCB Stackup Specifications
        6. 7.5.4.6 Grounding
      5. 7.5.5 SATA Board Design and Layout Guidelines
        1. 7.5.5.1 SATA Interface Schematic
        2. 7.5.5.2 Compatible SATA Components and Modes
        3. 7.5.5.3 PCB Stackup Specifications
        4. 7.5.5.4 Routing Specifications
      6. 7.5.6 PCIe Board Design and Layout Guidelines
        1. 7.5.6.1 PCIe Connections and Interface Compliance
          1. 7.5.6.1.1 Coupling Capacitors
          2. 7.5.6.1.2 Polarity Inversion
        2. 7.5.6.2 Non-standard PCIe connections
          1. 7.5.6.2.1 PCB Stackup Specifications
          2. 7.5.6.2.2 Routing Specifications
            1. 7.5.6.2.2.1 Impedance
            2. 7.5.6.2.2.2 Differential Coupling
            3. 7.5.6.2.2.3 Pair Length Matching
        3. 7.5.6.3 LJCB_REFN/P Connections
    6. 7.6 Clock Routing Guidelines
      1. 7.6.1 32-kHz Oscillator Routing
      2. 7.6.2 Oscillator Ground Connection
    7. 7.7 DDR2/DDR3 Board Design and Layout Guidelines
      1. 7.7.1 DDR2/DDR3 General Board Layout Guidelines
      2. 7.7.2 DDR2 Board Design and Layout Guidelines
        1. 7.7.2.1 Board Designs
        2. 7.7.2.2 DDR2 Interface
          1. 7.7.2.2.1  DDR2 Interface Schematic
          2. 7.7.2.2.2  Compatible JEDEC DDR2 Devices
          3. 7.7.2.2.3  PCB Stackup
          4. 7.7.2.2.4  Placement
          5. 7.7.2.2.5  DDR2 Keepout Region
          6. 7.7.2.2.6  Bulk Bypass Capacitors
          7. 7.7.2.2.7  High-Speed Bypass Capacitors
          8. 7.7.2.2.8  Net Classes
          9. 7.7.2.2.9  DDR2 Signal Termination
          10. 7.7.2.2.10 VREF Routing
        3. 7.7.2.3 DDR2 CK and ADDR_CTRL Routing
      3. 7.7.3 DDR3 Board Design and Layout Guidelines
        1. 7.7.3.1  Board Designs
        2. 7.7.3.2  DDR3 EMIF
        3. 7.7.3.3  DDR3 Device Combinations
        4. 7.7.3.4  DDR3 Interface Schematic
          1. 7.7.3.4.1 32-Bit DDR3 Interface
          2. 7.7.3.4.2 16-Bit DDR3 Interface
        5. 7.7.3.5  Compatible JEDEC DDR3 Devices
        6. 7.7.3.6  PCB Stackup
        7. 7.7.3.7  Placement
        8. 7.7.3.8  DDR3 Keepout Region
        9. 7.7.3.9  Bulk Bypass Capacitors
        10. 7.7.3.10 High-Speed Bypass Capacitors
          1. 7.7.3.10.1 Return Current Bypass Capacitors
        11. 7.7.3.11 Net Classes
        12. 7.7.3.12 DDR3 Signal Termination
        13. 7.7.3.13 VREF_DDR Routing
        14. 7.7.3.14 VTT
        15. 7.7.3.15 CK and ADDR_CTRL Topologies and Routing Definition
          1. 7.7.3.15.1 Four DDR3 Devices
            1. 7.7.3.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 7.7.3.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 7.7.3.15.2 Two DDR3 Devices
            1. 7.7.3.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 7.7.3.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 7.7.3.15.3 One DDR3 Device
            1. 7.7.3.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 7.7.3.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        16. 7.7.3.16 Data Topologies and Routing Definition
          1. 7.7.3.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 7.7.3.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        17. 7.7.3.17 Routing Specification
          1. 7.7.3.17.1 CK and ADDR_CTRL Routing Specification
          2. 7.7.3.17.2 DQS and DQ Routing Specification
  8. 8Device and Documentation Support
    1. 8.1  Device Nomenclature
      1. 8.1.1 Standard Package Symbolization
      2. 8.1.2 Device Naming Convention
    2. 8.2  Tools and Software
    3. 8.3  Documentation Support
      1. 8.3.1 FCC Warning
      2. 8.3.2 Information About Cautions and Warnings
    4. 8.4  Receiving Notification of Documentation Updates
    5. 8.5  Related Links
    6. 8.6  Community Resources
    7. 8.7  商标
    8. 8.8  静电放电警告
    9. 8.9  Export Control Notice
    10. 8.10 Glossary
  9. 9Mechanical Packaging and Orderable Information
    1. 9.1 Mechanical Data

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Power Supply Sequences

This section describes the power-up and power-down sequence required to ensure proper device operation. The power supply names described in this section comprise a superset of a family of compatible devices. Some members of this family will not include a subset of these power supplies and their associated device modules. Refer to the Section 4.2, Pin Attributes of the Section 4, Terminal Configuration and Functions to determine which power supplies are applicable.

Figure 5-5 and Figure 5-6, describes the device power sequencing.

DRA75P DRA74P SPRS85v_ELCH_01.gifFigure 5-5 Recommended Power-Up Sequencing
  1. Time stamps:
    • T0 = 0 ms; T1 = 0.55 ms; T2 = 1.1 ms; T3 = 1.65 ms; T4 = 2.2 ms; T5 = 2.75 ms; T6 = 3.3 ms; T7 = 5.85 ms; T8 = 6.4 ms; T9 = 8.4 ms. All “Tn” markers show total elapsed time from T0.
  2. Terminology:
    • VOPR MIN = Minimum Operational Voltage level that ensures device functionality and specified performance per Section 5.4, Recommended Operating Conditions.
    • Ramp Up = transition time from VOFF to VOPR MIN.
  3. General timing diagram items:
    • Grey shaded areas show valid transition times for supplies between VOPR MIN and VOFF.
    • Dashed horizontal lines are not valid ramp times but show alternate transition times based upon common sources and clarified in associated note.
    • Dashed vertical lines show approximate elapse times based upon TI recommended PMIC power sequencer circuit performance.
  4. vddshv5, vdd_rtc, and vdda_rtc domains:
    • If RTC mode is used, then vdda_rtc, vdd_rtc and vddshv5 must be individually powered with separate power supplies and cannot be combined with other rails.
    • If RTC-mode is not supported then the following combinations are approved:
      • vdda_rtc can be combined with vdds18v
      • vdd_rtc can be combined with vdd
      • vddshv5 can be combined with other 1.8 V or 3.3 V vddshvn rails
      If combinations listed above are not followed then sequencing for these 3 voltage rails should follow the RTC mode timing requirements.
  5. vdda_* rails should not be combined with vdds18v_* for best performance to avoid transient switching noise impacts on analog domains. vdda_* should not ramp-up before vdds18v_* but could ramp concurrently if design ensures final operational voltage will not be reached until after vdds18v. The preferred sequence is to follow all vdds18v_* to ensure circuit components and PCB design do not cause an inadvertent violation.
  6. vdds_ddr* should not ramp-up before vdds18v_*. The preferred sequence has vdds_ddr1 following vdds18v_* to ensure circuit components and PCB design do not cause an inadvertent violation. vdds_ddr1 can ramp-up before, concurrently or after vdda_*, there are no dependencies between vdds_ddr1 and vdda_* domains.
    • vdd should not ramp-up before vdds18v_* or vdds_ddr* domains have reached VOPR MIN.
    • vdd_mpu, vdd_iva, vdd_gpu, vdd_dspeve domains should follow vdd core supply as preferred sequence. If vdd_mpu, vdd_iva, vdd_gpu, vdd_dspeve domains ramp concurrently or quicker than vdd core, then vdd core must remain at least 150 mV greater than vdd_mpu, vdd_iva, vdd_gpu, vdd_dspeve domains during ramp. Circuit design (components and PCB) must ensure vdd reaches final operational voltage before any of the vdd_mpu, vdd_iva, vdd_gpu, vdd_dspeve domains.
    • VDDA_PHY group should not be combined with VDDA_PLL group to avoid transient switching noise impacts.
    • vddshv[1-4, 6, 7, 9-11] domains:
      • If 1.8 V I/O signaling is needed, then 1.8 V must be sourced from common vdds18v supply and ramp up concurrently with vdds18v.
      • If 3.3 V I/O signaling is needed, then 3.3 V vddshvx rails must ramp up after vdd_mpu, vdd_iva, vdd_gpu, vdd_dspeve, and VDDA_PHY group domains.
    • vdda33v_usb[1-2] domain:
      • If USB1 and USB2 interfaces are used, should be supplied from independent analog supply.
      • If USB1/USB2 interface is not used, could be connected to VSS/GND if both conditions are met:
        • USB1/USB2 diff pair (usb1_dm/usb1_dp; usb2_dm/usb2_dp) pins are left unconnected
        • vdda_usb1 and/or vdda_usb2 PHY is not energized
    • vddshv8 shows two ramp up options for 1.8 V I/O or 3.3 V I/O or SD Card operation:
      • If 1.8 V I/O signaling is needed, then vddshv8 must ramp up after vdd and before or concurrently with 3.3 V vddshv* rails.
      • If 3.3 V I/O signaling is needed, then vddshv8 must be combined with other 3.3 V vddshv* rails.
      • If SD Card operation is needed, then vddshv8 must be sourced from a dual voltage (3.3 V / 1.8 V) power source per SDIO specifications and ramp up concurrently with 3.3 V vddshv* rails.
    • Pulse duration: rtc_porz must remain low 1ms after vdda_rtc, vddshv5, and vdd_rtc are ramped and stable or can be de-asserted before but no later than porz. The FUNK_32K_CLK source must be stable and at a valid frequency 1 ms prior to de-asserting rtc_porz high.
    • porz must remain asserted low until both of the following conditions are met:
      • Minimum of 12 × P, where P = 1 / (SYS_CLK1 / 610), units in ns.
      • All device supply rails reach stable operational levels.
    • Setup time: sysboot[15:0] pins must be valid 2P(14) before porz is de-asserted high.
    • Hold time: sysboot[15:0] pins must be valid 15P(14) after porz is de-asserted high.
    • rstoutn will be set high after global reset, due to porz, is de-asserted following an internal 2 ms delay. rstoutn is only valid after vddshv3 reaches an operational level. If used as a peripheral component reset, it should be AND gated with porz to avoid possible reset glitches during power up.
    DRA75P DRA74P SPRS85v_ELCH_02.gifFigure 5-6 Recommended Power-Down Sequencing
    1. Time stamps:
      • T0 = 0 ms, T1 > 100 μs, T2 = 0.5 ms, T3 = 1.0 ms, T4 = 1.5 ms; V1 = 2.7 V. All “Tn” markers are intended to show elapsed times from T0. Delta time: Δ TD1 > 100 μs.
    2. Terminology:
      • VOPR MIN = Minimum Operational Voltage level that ensures device functionality and specified performance per Section 5.4, Recommended Operating Conditions.
      • VOFF = OFF Voltage level is defined to be less than 0.6 V where any current draw has no impact to POH.
      • Ramp Down = transition time from VOPR MIN to VOFF and is slew rate independent.
    3. General timing diagram items:
      • Grey shaded areas show valid transition times for supplies between VOPR MIN and VOFF.
      • Dashed horizontal lines are not valid ramp times but show alternate transition times based upon common sources and clarified in associated note.
      • Dashed vertical lines show approximate elapse times based upon TI recommended PMIC power-down sequencer circuit performance.
    4. porz signals must be asserted low for 100 µs min to ensure SoC is set to a safe functional state before any voltage begins to ramp down.
    5. vddshv* domains supplied by 3.3 V:
      • must remain greater than 2.7 V to enable Dual Voltage GPIO selector circuit operation for 100 µs min after porz is asserted low.
      • must be in first group of supplies ramping down after porz has been asserted low for 100 µs min.
      • must not exceed vdds18v by more than 2 V during ramp down, see Figure 5-10 “vdds18v and vdda_* Discharge Relationship”.
    6. vddshv* domains supplied by 1.8 V:
      • must ramp down concurrently with vdds18v and be sourced from the same vdds18v supply.
    7. vddshv8 domain:
      • must be in first group of supplies to ramp down after porz has been asserted low for 100 µs min.
      • if SDIO operation is needed, must be sourced from independent power resource that can provide dual voltage (3.3 V / 1.8 V) operation as required to be compliant to SDIO specification
      • if SDIO operation is not needed, must be grouped and ramped down with other vddshv* domains as noted above.
    8. RTC domains (vddshv5, vdd_rtc, and vdda_rtc):
      • If RTC mode is used:
        • rtc_porz can be asserted low before porz and RTC domains can be ramped down after 100 µs elapsed time.
        • must be sourced from independent supplies and must not be combined with other rails.
        • timing diagram shows this mode of operation.
      • If RTC mode is not used, then:
        • rtc_porz must be connected to porz signal.
        • vddshv5 must be grouped and ramped down with other vddshv* domains as noted above.
        • vdd_rtc must be grouped and ramped down with vdd.
        • vdda_rtc must be grouped and ramped down with either VDDA_PHY group or vdds18v.
    9. vdda_* domains:
      • should not be combined with vdds18v for best performance to avoid transient switching noise impacts on analog domains.
      • can ramp down before or concurrently with vdds18v.
      • must satisfy the vdds18v and vdda_* Discharge Relationship (see Figure 5-10) if vdda_* disable point is later or discharge rate is slower than vdds18v.
      • can ramp down before, concurrently or after vdds_ddr*, there is no dependency between these supplies.
    10. vdda33v_usb* domains:
      • can start ramping down 100 µs after low assertion of porz
      • can ramp down concurrently or before VDDA_PHY group
    11. vdd_dspeve, vdd_gpu, vdd_iva, vdd_mpu domains can ramp down before or concurrently with vdd.
    12. vdd can ramp down concurrently or after with vdd_dspeve, vdd_gpu, vdd_iva, vdd_mpu domains.
    13. vdds_ddr* domains:
      • should ramp down after vdd begins ramping down.
    14. vdds18v domain:
      • should maintain VOPR MIN (VNOM -5% = 1.71 V) until all other supplies start to ramp down.
      • must satisfy the vdds18v versus vddshv[1-7, 9-11] Discharge Relationship (see Figure 5-8) if vddshv* is operating at 3.3 V
      • must satisfy the vdds18v and vdds_ddr* Discharge Relationship (see Figure 5-9) if vdds_ddr* discharge rate is slower than vdds18v.

    Figure 5-7 describes the RTC-mode power sequencing.

    DRA75P DRA74P SPRS85v_ELCH_03.gifFigure 5-7 RTC Mode Sequencing
    1. Grey shaded areas are windows where it is valid to ramp the voltage rail.
    2. Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.
    3. vdd must ramp down after or at the same time as vdd_mpu, vdd_gpu, vdd_dspeve and vdd_iva.
    4. vdd_mpu, vdd_gpu, vdd_dspeve, vdd_iva can be ramped at the same time or can be staggered.
    5. vdd must ramp up before or at the same time as vdd_mpu, vdd_gpu, vdd_dspeve and vdd_iva.
    6. If any of the vddshv[1-7,9-11] rails (not including vddshv8) are used as 1.8 V only, then these rails can be combined with vdds18v.
    7. vddshv8 is separated out to show support for dual voltage. If single voltage is used then vddshv8 can be combined with other vddshvn rails but vddshv8 must ramp down before vdd and must ramp up after vdd.
    8. If any of the vddshv[1-7,9-11] rails (not including vddshv8) are used as 1.8 V only, then these rails can be combined with vdds18v. vddshv[1-7,9-11] is allowed to ramp down at either of the two points shown in the timing diagram in either 1.8 V mode or in 3.3 V mode. If vddshv[1-7,9-11] ramps down at the later time in the diagram then the board design must guarantee that the vddshvn rail is never higher than 2.0 V above the vdds18v rail.
    9. vddshv8 is separated out to show support for dual voltage. If a dedicated LDO/supply source is used for vddshv8, then vddshv8 ramp down should occur at one of the two earliest points in the timing diagram. If vddshv8 is powered by the same supply source as the other vddshvn rails, then it is allowed to ramp down at either of the last two points in the timing diagram.

    Figure 5-8 describes vddshv[1-7,9-11] supplies falling before vdds18v supplies delta.

    DRA75P DRA74P SPRS85v_ELCH_06.gifFigure 5-8 vdds18v versus vddshv[1-7, 9-11] Discharge Relationship
    1. Vdelta MAX = 2 V.
    2. If vddshv8 is powered by the same supply source as the other vddshv[1-7,9-11] rails.

    If vdds18v and vdds_ddr* are disabled at the same time due to a loss of input power event or if vdds_ddr* discharges more slowly than vdds18v, analysis has shown no reliability impacts when the elapsed time period beginning with vdds18v dropping below 1.0 V and ending with vdds_ddr* dropping below 0.6 V is less than 10 ms (Figure 5-9).

    DRA75P DRA74P SPRS916_ELCH_04.gifFigure 5-9 vdds18v and vdds_ddr* Discharge Relationship(1)
    1. V1 > 1.0 V; V2 < 0.6 V; T1 < 10 ms.
    DRA75P DRA74P SPRS916_ELCH_05.gifFigure 5-10 vdds18v and vdda_* Discharge Relationship(3)
    1. vdda_* can be ≥ vdds18v, until vdds18v drops below 1.62 V.
    2. vdds18v must be ≥ vdda_*, until vdds18v reaches 0.6 V.
    3. V1 = 1.62 V; V2 < 0.6 V.

    Figure 5-8 through Figure 5-11 and associated notes described the device abrupt power down sequence.

    A ”loss of input power event” occurs when the system’s input power is unexpectedly removed. Normally, the recommended power-down sequence should be followed and can be accomplished within 1.5-2 ms of elapsed time. This is the typical range of elapsed time available following a loss of power event, see Section 7.3.7 for design recommendations. If sufficient elapse time is not provided, then an “abrupt” power down sequence can be supported without impacting POH reliability if all of the following conditions are met (Figure 5-11).

    DRA75P DRA74P SPRS916_ELCH_06.gifFigure 5-11 Abrupt Power-Down Sequencing(1)
    1. Time stamps:
      • V1 = 2.7 V; V2 = 3.3 V; V3 = 2.0 V; V4 = V5 = V6 = 0.6 V; V7 = V8 = 1.62 V; V9 = 1.3 V; V10 = 1.0 V; V11 = 0.0 V; Tdelta1 > 100 µs; Tdelta2 < 10 ms.
    2. Terminology:
      • VOPR MIN = Minimum Operational Voltage level that ensures device functionality and specified performance in Section 5.4, Recommended Operating Conditions table.
      • VOFF = OFF Voltage level is defined to be less than 0.6 V, where any current draw has no impact to POH.
      • Ramp Down = transition time from VOPR MIN to VOFF and is slew rate independent.
    3. General timing diagram items:
      • Grey shaded areas show valid transition times for supplies between VOPR MIN and VOFF.
      • Dashed vertical lines show approximate elapse times based upon TI recommended PMIC power-down sequencer circuit performance.
    4. porz and rtc_porz must be asserted low for 100 μs min to ensure SoC is set to a safe functional state before any voltage begins to ramp down.
      • Only if using RTC-mode with an independent RTC input power source, then rtc_porz can remain high and RTC-domains (vdd_rtc, vdda_rtc, and vddshv5) can remain energized while all other domains sourced from the system input power are powered down.
    5. vddshv[1-7, 9-11] domains supplied by 3.3 V:
      • must remain greater than 2.7 V to enable Dual Voltage GPIO selector circuit operation for 100 μs min, after porz is asserted low.
      • must not exceed vdds18v voltage level by more than 2 V during ramp down, until vdds18v drops below VOFF (0.6 V).
    6. vddshv[1-7, 9-11] domains supplied by 1.8 V must ramp down concurrently with vdds18v and be sourced from common vdds18v supply.
    7. vddshv8 supporting SD Card:
      • must be in first group of supplies to ramp down after porz has been asserted low for 100 µs min.
      • must be sourced from independent power resource that can provide dual voltage (3.3 V / 1.8 V) operation as required to be compliant to SDIO specification.
      • if SDIO operation is not needed, must be grouped with other vddshv[1-7, 9-11] domains.
    8. vdda33v_usb[1-2] domains must be in first group of supplies to ramp down after porz has been asserted low for 100 µs min.
    9. vdd_dspeve, vdd_gpu, vdd_iva, vdd_mpu, vdd, vdd_rtc, vdds_ddr1, vdda_* domains can all start to ramp down in any order after 100 µs low assertion of porz.
    10. vdds_ddr1 domains:
      • can remain at VOPR MIN or a level greater than vdds18v during ramp down.
      • elapsed time from vdds18v dropping below 1.0 V to vdds_ddr[1-3] dropping below 0.6 V must not exceed 10 ms.
    11. vdda_* domains:
      • can start to ramp down before or concurrently with vdds18v.
      • must not exceed vdds18v voltage level after vdds18v drops below 1.62 V until vdds18v drops below VOFF (0.6 V).
    12. vdds18v domain should maintain a minimum level of 1.62 V (VNOM – 10%) until vdd_dspeve and vdd start to ramp down.