SNLS266E May   2007  – March 2015 DP83848C , DP83848I , DP83848VYB , DP83848YB

PRODUCTION DATA.  

  1. 1Introduction
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3 Device Comparison
  4. 4Pin Configuration and Functions
    1. 4.1  Pin Layout
    2. 4.2  Package Pin Assignments
    3. 4.3  Serial Management Interface
    4. 4.4  Mac Data Interface
    5. 4.5  Clock Interface
    6. 4.6  LED Interface
    7. 4.7  JTAG Interface for DP83848I/VYB/YB
    8. 4.8  Reset and Power Down
    9. 4.9  Strap Options
    10. 4.10 10 Mb/s and 100 Mb/s PMD Interface
    11. 4.11 Special Connections
    12. 4.12 Power Supply Pins
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 DC Specifications
    6. 5.6 AC Timing Requirements
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Auto-Negotiation
        1. 6.3.1.1 Auto-Negotiation Pin Control
        2. 6.3.1.2 Auto-Negotiation Register Control
        3. 6.3.1.3 Auto-Negotiation Parallel Detection
        4. 6.3.1.4 Auto-Negotiation Restart
        5. 6.3.1.5 Enabling Auto-Negotiation Through Software
        6. 6.3.1.6 Auto-Negotiation Complete Time
      2. 6.3.2 Auto-MDIX
      3. 6.3.3 LED Interface
        1. 6.3.3.1 LEDs
        2. 6.3.3.2 LED Direct Control
      4. 6.3.4 Internal Loopback
      5. 6.3.5 BIST
      6. 6.3.6 Energy Detect Mode
    4. 6.4 Device Functional Modes
      1. 6.4.1 MII Interface
        1. 6.4.1.1 Nibble-wide MII Data Interface
        2. 6.4.1.2 Collision Detect
        3. 6.4.1.3 Carrier Sense
      2. 6.4.2 Reduced MII Interface
      3. 6.4.3  802.3 MII Serial Management Interface
        1. 6.4.3.1 Serial Management Register Access
        2. 6.4.3.2 Serial Management Access Protocol
        3. 6.4.3.3 Serial Management Preamble Suppression
      4. 6.4.4 10 Mb Serial Network Interface (SNI)
      5. 6.4.5 PHY Address
        1. 6.4.5.1 MII Isolate Mode
      6. 6.4.6 Half Duplex vs. Full Duplex
      7. 6.4.7 Reset Operation
        1. 6.4.7.1 Hardware Reset
        2. 6.4.7.2 Software Reset
    5. 6.5 Programming
      1. 6.5.1 Architecture
        1. 6.5.1.1 100BASE-TX Transmitter
          1. 6.5.1.1.1 Code-group Encoding and Injection
          2. 6.5.1.1.2 Scrambler
          3. 6.5.1.1.3 NRZ to NRZI Encoder
          4. 6.5.1.1.4 Binary to MLT-3 Convertor
        2. 6.5.1.2 100BASE-TX Receiver
          1. 6.5.1.2.1  Analog Front End
          2. 6.5.1.2.2  Digital Signal Processor
            1. 6.5.1.2.2.1 Digital Adaptive Equalization and Gain Control
            2. 6.5.1.2.2.2 Base Line Wander Compensation
          3. 6.5.1.2.3  Signal Detect
          4. 6.5.1.2.4  MLT-3 to NRZI Decoder
          5. 6.5.1.2.5  NRZI to NRZ
          6. 6.5.1.2.6  Serial to Parallel
          7. 6.5.1.2.7  Descrambler
          8. 6.5.1.2.8  Code-group Alignment
          9. 6.5.1.2.9  4B/5B Decoder
          10. 6.5.1.2.10 100BASE-TX Link Integrity Monitor
          11. 6.5.1.2.11 Bad SSD Detection
        3. 6.5.1.3 10BASE-T Transceiver Module
          1. 6.5.1.3.1  Operational Modes
            1. 6.5.1.3.1.1 Half Duplex Mode
            2. 6.5.1.3.1.2 Full Duplex Mode
          2. 6.5.1.3.2  Smart Squelch
          3. 6.5.1.3.3  Collision Detection and SQE
          4. 6.5.1.3.4  Carrier Sense
          5. 6.5.1.3.5  Normal Link Pulse Detection/Generation
          6. 6.5.1.3.6  Jabber Function
          7. 6.5.1.3.7  Automatic Link Polarity Detection and Correction
          8. 6.5.1.3.8  Transmit and Receive Filtering
          9. 6.5.1.3.9  Transmitter
          10. 6.5.1.3.10 Receiver
    6. 6.6 Memory
      1. 6.6.1 Register Block
        1. 6.6.1.1 Register Definition
          1. 6.6.1.1.1 Basic Mode Control Register (BMCR)
          2. 6.6.1.1.2 Basic Mode Status Register (BMSR)
          3. 6.6.1.1.3 PHY Identifier Register #1 (PHYIDR1)
          4. 6.6.1.1.4 PHY Identifier Register #2 (PHYIDR2)
          5. 6.6.1.1.5 Auto-Negotiation Advertisement Register (ANAR)
          6. 6.6.1.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
          7. 6.6.1.1.7 Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page)
          8. 6.6.1.1.8 Auto-Negotiate Expansion Register (ANER)
          9. 6.6.1.1.9 Auto-Negotiation Next Page Transmit Register (ANNPTR)
        2. 6.6.1.2 Extended Registers
          1. 6.6.1.2.1  PHY Status Register (PHYSTS)
          2. 6.6.1.2.2  MII Interrupt Control Register (MICR)
          3. 6.6.1.2.3  MII Interrupt Status and Misc. Control Register (MISR)
          4. 6.6.1.2.4  False Carrier Sense Counter Register (FCSCR)
          5. 6.6.1.2.5  Receiver Error Counter Register (RECR)
          6. 6.6.1.2.6  100 Mb/s PCS Configuration and Status Register (PCSR)
          7. 6.6.1.2.7  RMII and Bypass Register (RBR)
          8. 6.6.1.2.8  LED Direct Control Register (LEDCR)
          9. 6.6.1.2.9  PHY Control Register (PHYCR)
          10. 6.6.1.2.10 10 Base-T Status/Control Register (10BTSCR)
          11. 6.6.1.2.11 CD Test and BIST Extensions Register (CDCTRL1)
          12. 6.6.1.2.12 Energy Detect Control (EDCR)
  7. 7Application, Implementation, and Layout
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
        1. 7.2.1.1 TPI Network Circuit
        2. 7.2.1.2 Clock IN (X1) Requirements
          1. 7.2.1.2.1 Oscillator
          2. 7.2.1.2.2 Crystal
        3. 7.2.1.3 Power Feedback Circuit
          1. 7.2.1.3.1 Power Down and Interrupt
            1. 7.2.1.3.1.1 Power Down Control Mode
            2. 7.2.1.3.1.2 Interrupt Mechanisms
        4. 7.2.1.4 Magnetics
        5. 7.2.1.5 ESD Protection
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 MAC Interface (MII/RMII)
          1. 7.2.2.1.1 Termination Requirement
          2. 7.2.2.1.2 Recommended Maximum Trace Length
        2. 7.2.2.2 Calculating Impedance
          1. 7.2.2.2.1 Microstrip Impedance - Single-Ended
          2. 7.2.2.2.2 Stripline Impedance - Single Ended
          3. 7.2.2.2.3 Microstrip Impedance - Differential
          4. 7.2.2.2.4 Stripline Impedance - Differential
      3. 7.2.3 Application Curves
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
        1. 7.3.1.1 PCB Layout Considerations
        2. 7.3.1.2 PCB Layer Stacking
      2. 7.3.2 Layout Example
    4. 7.4 Power Supply Recommendations
  8. 8Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Related Links
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
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订购信息

4 Pin Configuration and Functions

The DP83848VYB pins are classified into the following interface categories (each interface is described in the sections that follow):

  • Serial Management Interface
  • MAC Data Interface
  • Clock Interface
  • LED Interface
  • JTAG Interface
  • Reset and Power Down
  • Strap Options
  • 10/100 Mb/s PMD Interface
  • Special Connect Pins
  • Power and Ground pins

NOTE

Strapping pin option. See Section 4.9 for strap definitions.

All DP83848VYB signal pins are I/O cells regardless of the particular use. The definitions below define the functionality of the I/O cells for each pin.

    Type: IInput
    Type: OOutput
    Type: I/OInput/Output
    Type: ODOpen Drain
    Type: PD,PU Internal Pulldown/Pullup
    Type: SStrapping Pin (All strap pins have weak internal pullups or pulldowns. If the default strap value is to be changed then an external 2.2 kΩ resistor should be used. See Section 4.9 for details.)

4.1 Pin Layout

PTB Package
48-Pin HLQFP
Top View

DP83848C DP83848I DP83848VYB DP83848YB 30011755.png

4.2 Package Pin Assignments

VBH48A PIN # PIN NAME VBH48A PIN # PIN NAME
1 TX_CLK 26 LED_ACT/COL/AN_EN
2 TX_EN 27 LED_SPEED/AN1
3 TXD_0 28 LED_LINK/AN0
4 TXD_1 29 RESET_N
5 TXD_2 30 MDIO
6 TXD_3/SNI_MODE 31 MDC
7 PWR_DOWN/INT 32 IOVDD33
8 TCK 33 X2
9 TDO 34 X1
10 TMS 35 IOGND
11 TRST# 36 DGND
12 TDI 37 PFBIN2
13 RD - 38 RX_CLK
14 RD + 39 RX_DV/MII_MODE
15 AGND 40 CRS/CRS_DV/LED_CFG
16 TD - 41 RX_ER/MDIX_EN
17 TD + 42 COL/PHYAD0
18 PFBIN1 43 RXD_0/PHYAD1
19 AGND 44 RXD_1/PHYAD2
20 RESERVED 45 RXD_2/PHYAD3
21 RESERVED 46 RXD_3/PHYAD4
22 AVDD33 47 IOGND
23 PFBOUT 48 IOVDD33
24 RBIAS 49 GNDPAD
25 CLK_OUT

4.3 Serial Management Interface

SIGNAL NAME TYPE PIN # DESCRIPTION
MDC I 31 MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO management data input/output serial interface which may be asynchronous to transmit and receive clocks. The maximum clock rate is 25 MHz with no minimum clock rate.
MDIO I/O 30 MANAGEMENT DATA I/O: Bi-directional management instruction/data signal that may be sourced by the station management entity or the PHY. This pin requires a 1.5 kΩ pullup resistor.

4.4 Mac Data Interface

SIGNAL NAME TYPE PIN # DESCRIPTION
TX_CLK O 1 MII TRANSMIT CLOCK: 25 MHz Transmit clock output in 100 Mb/s mode or 2.5 MHz in 10 Mb/s mode derived from the 25 MHz reference clock.
Unused in RMII mode. The device uses the X1 reference clock input as the 50 MHz reference for both transmit and receive.
SNI TRANSMIT CLOCK: 10 MHz Transmit clock output in 10 Mb SNI mode. The MAC should source TX_EN and TXD_0 using this clock.
TX_EN I, PD 2 MII TRANSMIT ENABLE: Active high input indicates the presence of valid data inputs on TXD[3:0].
RMII TRANSMIT ENABLE: Active high input indicates the presence of valid data on TXD[1:0].
SNI TRANSMIT ENABLE: Active high input indicates the presence of valid data on TXD_0.
TXD_0
TXD_1
TXD_2
TXD_3		 I
 
 
S, I, PD		 3
4
5
6		 MII TRANSMIT DATA: Transmit data MII input pins, TXD[3:0], that accept data synchronous to the TX_CLK (2.5 MHz in 10 Mb/s mode or 25 MHz in 100 Mb/s mode).
RMII TRANSMIT DATA: Transmit data RMII input pins, TXD[1:0], that accept data synchronous to the 50 MHz reference clock.
SNI TRANSMIT DATA: Transmit data SNI input pin, TXD_0, that accept data synchronous to the TX_CLK (10 MHz in 10 Mb/s SNI mode).
RX_CLK O 38 MII RECEIVE CLOCK: Provides the 25 MHz recovered receive clocks for 100 Mb/s mode and 2.5 MHz for 10 Mb/s mode.
Unused in RMII mode. The device uses the X1 reference clock input as the 50 MHz reference for both transmit and receive.
SNI RECEIVE CLOCK: Provides the 10 MHz recovered receive clocks for 10 Mb/s SNI mode.
RX_DV S, O, PD 39 MII RECEIVE DATA VALID: Asserted high to indicate that valid data is present on the corresponding RXD[3:0]. Mll mode by default with internal pulldown.
RMII Synchronous RECEIVE DATA VALID:This signal provide the RMII Receive Data Valid indication independent of Carrier Sense.
This pin is not used in SNI mode.
RX_ER S, O, PU 41 MII RECEIVE ERROR: Asserted high synchronously to RX_CLK to indicate that an invalid symbol has been detected within a received packet in 100 Mb/s mode.
RMII RECEIVE ERROR: Asserted high synchronously to X1 whenever an invalid symbol is detected, and CRS_DV is asserted in 100 Mb/s mode.
This pin is not required to be used by a MAC in either MII or RMII mode, since the Phy is required to corrupt data on a receive error.
This pin is not used in SNI mode.
RXD_0
RXD_1
RXD_2
RXD_3		 S, O, PD 43
44
45
46		 MII RECEIVE DATA: Nibble wide receive data signals driven synchronously to the RX_CLK, 25 MHz for 100 Mb/s mode, 2.5 MHz for 10 Mb/s mode). RXD[3:0] signals contain valid data when RX_DV is asserted.
RMII RECEIVE DATA: 2-bits receive data signals, RXD[1:0], driven synchronously to the X1 clock, 50 MHz.
SNI RECEIVE DATA: Receive data signal, RXD_0, driven synchronously to the RX_CLK. RXD_0 contains valid data when CRS is asserted. RXD[3:1] are not used in this mode.
CRS/CRS_DV S, O, PU 40 MII CARRIER SENSE: Asserted high to indicate the receive medium is non-idle.
RMII CARRIER SENSE/RECEIVE DATA VALID: This signal combines the RMII Carrier and Receive Data Valid indications. For a detailed description of this signal, see the RMII Specification.
SNI CARRIER SENSE: Asserted high to indicate the receive medium is non-idle. It is used to frame valid receive data on the RXD_0 signal.
COL S, O, PU 42 MII COLLISION DETECT: Asserted high to indicate detection of a collision condition (simultaneous transmit and receive activity) in 10 Mb/s and 100 Mb/s Half Duplex Modes.
While in 10BASE-T Half Duplex mode with heartbeat enabled this pin is also asserted for a duration of approximately 1µs at the end of transmission to indicate heartbeat (SQE test).
In Full Duplex Mode, for 10 Mb/s or 100 Mb/s operation, this signal is always logic 0. There is no heartbeat function during 10 Mb/s full duplex operation.
RMII COLLISION DETECT: Per the RMII Specification, no COL signal is required. The MAC will recover CRS from the CRS_DV signal and use that along with its TX_EN signal to determine collision.
SNI COLLISION DETECT: Asserted high to indicate detection of a collision condition (simultaneous transmit and receive activity) in 10 Mb/s SNI mode.

4.5 Clock Interface

SIGNAL NAME TYPE PIN # DESCRIPTION
X1 I 34 CRYSTAL/OSCILLATOR INPUT: This pin is the primary clock reference input for the DP83848C/I/VYB/YB and must be connected to a 25 MHz 0.005% (±50 ppm) clock source. The DP83848C/I/VYB/YB supports either an external crystal resonator connected across pins X1 and X2, or an external CMOS-level oscillator source connected to pin X1 only.
RMII REFERENCE CLOCK: This pin is the primary clock reference input for the RMII mode and must be connected to a 50 MHz 0.005% (±50 ppm) CMOS-level oscillator source.
X2 O 33 CRYSTAL OUTPUT: This pin is the primary clock reference output to connect to an external 25 MHz crystal resonator device. This pin must be left unconnected if an external CMOS oscillator clock source is used.
CLK_OUT O 25 25 MHz CLOCK OUTPUT:
In MII mode, this pin provides a 25 MHz clock output to the system.
In RMII mode, this pin provides a 50 MHz clock output to the system.
This allows other devices to use the reference clock from the DP83848VYB without requiring additional clock sources.

4.6 LED Interface

See Table 6-2 for LED Mode Selection.

SIGNAL NAME TYPE PIN # DESCRIPTION
LED_LINK S, O, PU 28 LINK LED: In Mode 1, this pin indicates the status of the LINK. The LED will be ON when Link is good.
LINK/ACT LED: In Mode 2 and Mode 3, this pin indicates transmit and receive activity in addition to the status of the Link. The LED will be ON when Link is good. It will blink when the transmitter or receiver is active.
LED_SPEED S, O, PU 27 SPEED LED: The LED is ON when device is in 100 Mb/s and OFF when in 10 Mb/s. Functionality of this LED is independent of mode selected.
LED_ACT/COL S, O, PU 26 ACTIVITY LED: In Mode 1, this pin is the Activity LED which is ON when activity is present on either Transmit or Receive.
COLLISION/DUPLEX LED: In Mode 2, this pin by default indicates Collision detection. For Mode 3, this LED output may be programmed to indicate Full-duplex status instead of Collision.

4.7 JTAG Interface for DP83848I/VYB/YB

SIGNAL NAME TYPE PIN #(1) DESCRIPTION
TCK I, PU 8 TEST CLOCK
This pin has a weak internal pullup.
TDI I, PU 12 TEST DATA INPUT
This pin has a weak internal pullup.
TDO O 9 TEST OUTPUT
TMS I, PU 10 TEST MODE SELECT
This pin has a weak internal pullup.
TRST# I, PU 11 TEST RESET: Active low asynchronous test reset.
This pin has a weak internal pullup.
(1) DP83848C does not support JTAG. Pins 8-12 should be left unconnected.

4.8 Reset and Power Down

SIGNAL NAME TYPE PIN # DESCRIPTION
RESET_N I, PU 29 RESET: Active Low input that initializes or re-initializes the DP83848VYB. Asserting this pin low for at least 1 µs will force a reset process to occur. All internal registers will re-initialize to their default states as specified for each bit in the Section 6.6 section. All strap options are re-initialized as well.
PWR_DOWN/INT I, PU 7 See Section 7.2.1.3.1 for detailed description.
The default function of this pin is POWER DOWN.
POWER DOWN: The pin is an active low input in this mode and should be asserted low to put the device in a Power Down mode.
INTERRUPT: The pin is an open drain output in this mode and will be asserted low when an interrupt condition occurs. Although the pin has a weak internal pullup, some applications may require an external pullup resister. Register access is required for the pin to be used as an interrupt mechanism. See Section 7.2.1.3.1.2 for more details on the interrupt mechanisms.

4.9 Strap Options

The DP83848VYB uses many of the functional pins as strap options. The values of these pins are sampled during reset and used to strap the device into specific modes of operation. The strap option pin assignments are defined below. The functional pin name is indicated in parentheses.

A 2.2 kΩ resistor should be used for pulldown or pullup to change the default strap option. If the default option is required, then there is no need for external pullup or pulldown resistors. Since these pins may have alternate functions after reset is deasserted, they should not be connected directly to VCC or GND.

SIGNAL NAME TYPE PIN # DESCRIPTION
PHYAD0 (COL)
PHYAD1 (RXD1_0)
PHYAD2 (RXD0_1)
PHYAD3 (RXD1_2)
PHYAD4 (RXD1_3)		 S, O, PU
S, O, PD		 42
43
44
45
46		 PHY ADDRESS [4:0]: The DP83848VYB provides five PHY address pins, the state of which are latched into the PHYCTRL register at system Hardware-Reset.
The DP83848VYB supports PHY Address strapping values 0 (<00000>) through 31 (<11111>).A PHY Adress of 0 puts the part into the Mll isolate Mode. The Mll isolate mode must be selected by strapping Phy Address 0; changing to Address 0 by register write will not put the Phy in the Mll isolate mode. Please refer to Section 6.4.5 for additional information.
PHYAD0 pin has weak internal pullup resistor.
PHYAD[4:1] pins have weak internal pulldown resistors.
AN_EN(LED_ACT/COL)
AN_1 (LED_SPEED)
AN_0 (LED_LINK)		 S, O, PU 26
27
28		 Auto-Negotiation Enable: When high, this enables Auto-Negotiation with the capability set by AN0 and AN1 pins. When low, this puts the part into Forced Mode with the capability set by AN0 and AN1 pins.
AN0 / AN1: These input pins control the forced or advertised operating mode of the DP83848VYB according to the following table. The value on these pins is set by connecting the input pins to GND (0) or VCC (1) through 2.2 kΩ resistors. These pins should NEVER be connected directly to GND or VCC.
The value set at this input is latched into the DP83848VYB at Hardware-Reset.
The float/pulldown status of these pins are latched into the Basic Mode Control Register and the Auto_Negotiation Advertisement Register during Hardware-Reset.
The default is 111 since the these pin have internal pullups.
 
AN_EN AN1 AN0 Forced Mode
0 0 0 10BASE-T, Half-Duplex
0 0 1 10BASE-T, Full-Duplex
0 1 0 100BASE-TX, Half-Duplex
0 1 1 100BASE-TX, Full-Duplex
AN_EN AN1 AN0 Advertised Mode
1 0 0 10BASE-T, Half/Full-Duplex
1 0 1 100BASE-TX, Half/Full-Duplex
1 1 0 10BASE-T, Half-Duplex,
100BASE-TX, Half-Duplex
1 1 1 10BASE-T, Half/Full-Duplex,
100BASE-TX, Half/Full-Duplex
MII_MODE (RX_DV)
SNI_MODE (TXD_3)		 S, O, PD 39
6		 MII MODE SELECT: This strapping option pair determines the operating mode of the MAC Data Interface. Default operation (No pullups) will enable normal MII Mode of operation. Strapping MII_MODE high will cause the device to be in RMII or SNI modes of operation, determined by the status of the SNI_MODE strap. Since the pins include internal pulldowns, the default values are 0.
The following table details the configurations:
 
MII_MODE SNI_MODE MAC Interface Mode
0 X MII Mode
1 0 RMII Mode
1 1 10 Mb SNI Mode
LED_CFG (CRS) S, O, PU 40 LED CONFIGURATION: This strapping option determines the mode of operation of the LED pins. Default is Mode 1. Mode 1 and Mode 2 can be controlled through the strap option. All modes are configurable through register access.
See Table 6-2 for LED Mode Selection.
MDIX_EN (RX_ER) S, O, PU 41 MDIX ENABLE: Default is to enable MDIX. This strapping option disables Auto-MDIX. An external pulldown will disable Auto-MDIX mode.

4.10 10 Mb/s and 100 Mb/s PMD Interface

SIGNAL NAME TYPE PIN # DESCRIPTION
TD-, TD+ I/O 16
17		 Differential common driver transmit output (PMD Output Pair). These differential outputs are automatically configured to either 10BASE-T or 100BASE-TX signaling.
IIn Auto-MDIX mode of operation, this pair can be used as the Receive Input pair.
These pins require 3.3-V bias for operation.
RD-, RD+ I/O 13
14		 Differential receive input (PMD Input Pair). These differential inputs are automatically configured to accept either 100BASE-TX or 10BASE-T signaling.
In Auto-MDIX mode of operation, this pair can be used as the Transmit Output pair.
These pins require 3.3-V bias for operation.

4.11 Special Connections

SIGNAL NAME TYPE PIN # DESCRIPTION
RBIAS I 24 Bias Resistor Connection: A 4.87 kΩ 1% resistor should be connected from RBIAS to GND.
PFBOUT O 23 Power Feedback Output: Parallel caps, 10 µF (Tantalum preferred) and 0.1 µF, should be placed close to the PFBOUT. Connect this pin to PFBIN1 (pin 18) and PFBIN2 (pin 37). See Section 7.2.1.3 for proper placement pin.
PFBIN1
PFBIN2		 I 18
37		 Power Feedback Input: These pins are fed with power from PFBOUT pin. A small capacitor of 0.1 µF should be connected close to each pin.(1)
RESERVED I/O 20, 21 RESERVED: These pins must be pulled-up through 2.2 kΩ resistors to AVDD33 supply.
(1) Note: Do not supply power to these pins other than from PFBOUT.

4.12 Power Supply Pins

SIGNAL NAME PIN # DESCRIPTION
IOVDD33 32, 38 I/O 3.3-V Supply
IOGND 35, 47 I/O Ground
DGND 36 Digital Ground
AVDD33 22 Analog 3.3-V Supply
AGND 15, 19 Analog Ground
GNDPAD 49 Ground PAD