ZHCSDF9 February   2015 DP83848-HT

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 描述
  4. 4 典型系统图
  5. 5 修订历史记录
  6. 6 Bare Die Information
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 DC Electrical Characteristics
    6. 7.6 AC Timing Specifications
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 100BASE-TX Transmitter
        1. 8.3.1.1 Code-Group Encoding and Injection
        2. 8.3.1.2 Scrambler
        3. 8.3.1.3 NRZ to NRZI Encoder
        4. 8.3.1.4 Binary to MLT-3 Convertor
      2. 8.3.2 100BASE-TX Receiver
        1. 8.3.2.1  Analog Front End
        2. 8.3.2.2  Digital Signal Processor
          1. 8.3.2.2.1 Digital Adaptive Equalization and Gain Control
          2. 8.3.2.2.2 Base Line Wander Compensation
        3. 8.3.2.3  Signal Detect
        4. 8.3.2.4  MLT-3 to NRZI Decoder
        5. 8.3.2.5  NRZI to NRZ
        6. 8.3.2.6  Serial to Parallel
        7. 8.3.2.7  Descrambler
        8. 8.3.2.8  Code-Group Alignment
        9. 8.3.2.9  4B/5B Decoder
        10. 8.3.2.10 100BASE-TX Link Integrity Monitor
        11. 8.3.2.11 Bad SSD Detection
      3. 8.3.3 10BASE-T Transceiver Module
        1. 8.3.3.1  Operational Modes
          1. 8.3.3.1.1 Half Duplex Mode
          2. 8.3.3.1.2 Full Duplex Mode
        2. 8.3.3.2  Smart Squelch
        3. 8.3.3.3  Collision Detection and SQE
        4. 8.3.3.4  Carrier Sense
        5. 8.3.3.5  Normal Link Pulse Detection/Generation
        6. 8.3.3.6  Jabber Function
        7. 8.3.3.7  Automatic Link Polarity Detection and Correction
        8. 8.3.3.8  Transmit and Receive Filtering
        9. 8.3.3.9  Transmitter
        10. 8.3.3.10 Receiver
      4. 8.3.4 Reset Operation
        1. 8.3.4.1 Hardware Reset
        2. 8.3.4.2 Software Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 MII Interface
        1. 8.4.1.1 Nibble-Wide MII Data Interface
        2. 8.4.1.2 Collision Detect
        3. 8.4.1.3 Carrier Sense
      2. 8.4.2 Reduced MII Interface
      3. 8.4.3 10 Mb Serial Network Interface (SNI)
      4. 8.4.4 802.3u MII Serial Management Interface
        1. 8.4.4.1 Serial Management Register Access
        2. 8.4.4.2 Serial Management Access Protocol
        3. 8.4.4.3 Serial Management Preamble Suppression
    5. 8.5 Programming
      1. 8.5.1 Auto-Negotiation
        1. 8.5.1.1 Auto-Negotiation Pin Control
        2. 8.5.1.2 Auto-Negotiation Register Control
        3. 8.5.1.3 Auto-Negotiation Parallel Detection
        4. 8.5.1.4 Auto-Negotiation Restart
        5. 8.5.1.5 Enabling Auto-Negotiation via Software
        6. 8.5.1.6 Auto-Negotiation Complete Time
      2. 8.5.2 Auto-MDIX
      3. 8.5.3 PHY Address
        1. 8.5.3.1 MII Isolate Mode
      4. 8.5.4 LED Interface
        1. 8.5.4.1 LEDs
        2. 8.5.4.2 LED Direct Control
      5. 8.5.5 Half Duplex vs Full Duplex
      6. 8.5.6 Internal Loopback
      7. 8.5.7 BIST
    6. 8.6 Register Maps
      1. 8.6.1 Register Block
      2. 8.6.2 Register Definition
        1. 8.6.2.1 Basic Mode Control Register (BMCR)
        2. 8.6.2.2 Basic Mode Status Register (BMSR)
        3. 8.6.2.3 PHY Identifier Register 1 (PHYIDR1)
        4. 8.6.2.4 PHY Identifier Register 2 (PHYIDR2)
        5. 8.6.2.5 Auto-Negotiation Advertisement Register (ANAR)
        6. 8.6.2.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
        7. 8.6.2.7 Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page)
        8. 8.6.2.8 Auto-Negotiate Expansion Register (ANER)
        9. 8.6.2.9 Auto-Negotiation Next Page Transmit Register (ANNPTR)
      3. 8.6.3 Extended Registers
        1. 8.6.3.1  PHY Status Register (PHYSTS)
        2. 8.6.3.2  MII Interrupt Control Register (MICR)
        3. 8.6.3.3  MII Interrupt Status and Miscellaneous Control Register (MISR)
        4. 8.6.3.4  False Carrier Sense Counter Register (FCSCR)
        5. 8.6.3.5  Receiver Error Counter Register (RECR)
        6. 8.6.3.6  100 Mb/s PCS Configuration and Status Register (PCSR)
        7. 8.6.3.7  RMII and Bypass Register (RBR)
        8. 8.6.3.8  LED Direct Control Register (LEDCR)
        9. 8.6.3.9  PHY Control Register (PHYCR)
        10. 8.6.3.10 10Base-T Status/Control Register (10BTSCR)
        11. 8.6.3.11 CD Test and BIST Extensions Register (CDCTRL1)
        12. 8.6.3.12 Energy Detect Control (EDCR)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Clock Requirements
        2. 9.2.1.2 Magnetics
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 TPI Network Circuit
        2. 9.2.2.2 Clock In (X1) Requirements
          1. 9.2.2.2.1 Oscillator
          2. 9.2.2.2.2 Crystal
        3. 9.2.2.3 Power Feedback Circuit
        4. 9.2.2.4 Power Down and Interrupt
          1. 9.2.2.4.1 Power-Down Control Mode
          2. 9.2.2.4.2 Interrupt Mechanisms
        5. 9.2.2.5 Energy Detect Mode
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Layer Stacking
    2. 11.2 Layout Example
    3. 11.3 ESD Protection
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档
    2. 12.2 商标
    3. 12.3 静电放电警告
    4. 12.4 术语表
  13. 13机械封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
  • KGD|0
散热焊盘机械数据 (封装 | 引脚)
订购信息

12 器件和文档支持

12.1 文档支持

12.1.1 相关文档

本文档应结合以下文档一块使用，这样有助于您设计 PHYTER 产品：

  • 《DP83848C/I/YB 原理图》（文献编号：SNLR019）
  • 《DP83848C/I/YB 物料清单》（文献编号：SNLR020）
  • 《DP83848C/I/YB 用户指南》（文献编号：SNLU094）
  • 《DP83848C/I/YB 布局》（文献编号：SNLC032）

12.2 商标

PHYTER is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.3 静电放电警告

esds-image

这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损伤。

12.4 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、首字母缩略词和定义。