DLPS206 May   2021 DLPC7540

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Electrical Characteristics
    6. 6.6  Pin Electrical Characteristics
    7. 6.7  DMD HSSI Electrical Characteristics
    8. 6.8  DMD Low-Speed LVDS Electrical Characteristics
    9. 6.9  V-by-One Interface Electrical Characteristics
    10. 6.10 FPD-Link LVDS Electrical Characteristics
    11. 6.11 USB Electrical Characteristics
    12. 6.12 System Oscillator Timing Requirements
    13. 6.13 Power Supply and Reset Timing Requirements
    14. 6.14 DMD HSSI Timing Requirements
    15. 6.15 DMD Low-Speed LVDS Timing Requirements
    16. 6.16 V-by-One Interface General Timing Requirements
    17. 6.17 FPD-Link Interface General Timing Requirements
    18. 6.18 Source Frame Timing Requirements
    19. 6.19 Synchronous Serial Port Interface Timing Requirements
    20. 6.20 Master and Slave I2C Interface Timing Requirements
    21. 6.21 Programmable Output Clock Timing Requirements
    22. 6.22 JTAG Boundary Scan Interface Timing Requirements (Debug Only)
    23. 6.23 JTAG ARM Multi-Ice Interface Timing Requirements (Debug Only)
    24. 6.24 Multi-Trace ETM Interface Timing Requirements
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Sources
      2. 7.3.2 Processing Delays
      3. 7.3.3 FPD-Link Interface
      4. 7.3.4 V-by-One interface
      5. 7.3.5 DMD (HSSI) Interface
      6. 7.3.6 Program Memory Flash Interface
      7. 7.3.7 GPIO Supported Functionality
      8. 7.3.8 Debug Support
    4. 7.4 Device Operational Modes
      1. 7.4.1 Standby Mode
      2. 7.4.2 Active Mode
        1. 7.4.2.1 Normal Configuration
        2. 7.4.2.2 Low Latency Configuration
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Management
    2. 9.2 Hot Plug Usage
    3. 9.3 Power Supplies for Unused Input Source Interfaces
    4. 9.4 Power Supplies
      1. 9.4.1 1.15-V Power Supplies
      2. 9.4.2 1.21V Power Supply
      3. 9.4.3 1.8-V Power Supplies
      4. 9.4.4 3.3-V Power Supplies
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1  General Layout Guidelines
      2. 10.1.2  Power Supply Layout Guidelines
      3. 10.1.3  Layout Guidelines for Internal Controller PLL Power
      4. 10.1.4  Layout Guideline for DLPC7540 Reference Clock
        1. 10.1.4.1 Recommended Crystal Oscillator Configuration
      5. 10.1.5  V-by-One Interface Layout Considerations
      6. 10.1.6  FPD-Link Interface Layout Considerations
      7. 10.1.7  USB Interface Layout Considerations
      8. 10.1.8  DMD Interface Layout Considerations
      9. 10.1.9  General Handling Guidelines for Unused CMOS-Type Pins
      10. 10.1.10 Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
    2. 10.2 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1 Device Markings
        2. 11.1.2.2 Package Data
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
      1. 11.4.1 Video Timing Parameter Definitions
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum

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6.19 Synchronous Serial Port Interface Timing Requirements

For SSP0, SSP1 and SSP2(1)(2)
PARAMETERMINMAXUNIT
SSP Master
fclockClock frequency, SSPx_CLK
50% to 50% reference points0.3839.0MHz
tclockClock Period, SSPx_CLK50% to 50% reference points25.63632ns
tw(L)Pulse duration low, SSPx_CLK
50% to 50% reference points12.0ns
tw(H)Pulse duration high, SSPx_CLK
50% to 50% reference points12.0ns
tdelayOutput Delay – SSPx_TXD (MOSI)
-2.52.5ns
tsuSetup time – SSPx_RXD (MISO)
50% to 50% reference points15.0ns
thhold time – SSPx_RXD (MISO)
50% to 50% reference points0ns
ttTransition time (tr and tf- SSPx_RXD20% to 80% reference points1.5ns
tclkjitClock Jitter, SSPx_CLK300ps
tdelay∆Clock output delay ∆ { | tw(H) - tw(L) | }500ps
SSP Slave
tdelayOutput Delay – SSPx_TXD (MOSI)
015ns
tsuSetup time – SSPx_RXD (MISO)
50% to 50% reference points2.5ns
thhold time – SSPx_RXD (MISO)
50% to 50% reference points2.5ns
(1) The DLPC7540 SPI interfaces support SPI Modes 0, 1, 2, and 3 (that is, both clock polarities and both clock phases) as shown in Table 6-2 and Figure 6-16. As such, each SPI interface configuration must be setup to match the SPI mode being used.
(2) In most SPI applications, one clock edge is used by both master and slave devices for transmitting data while the other edge is use by both for sampling received data. This is referred to as Standard SPI Protocol. To maximize the SPI_CLK frequency potential, SPI masters can alternatively be designed to sample the data in (MISO) bit on the same clock edge used to transmit the next data out (MOSI) bit. This is referred to as Enhanced SPI Protocol. The DLPC7540 SPI master implementation supports both protocols (part of SPI interface configuration), however, to be able to use the "Enhanced SPI Protocol", the slave device must meet the requirement shown in Figure 6-17.
Table 6-2 SPI Clocking Modes
SPI Clocking ModeSPI Clock PolaritySPI Clock Phase
000
101
210
311
GUID-E3A09DBB-2938-457A-BFFD-F6FFDC424C8A-low.gifFigure 6-16 Timing Diagram for SPI Clocking Modes
GUID-EEEE1700-48A6-406B-86E7-07EA5CEDB49A-low.gifFigure 6-17 Requirement for Enhanced SPI Protocol
GUID-DEFAF8AC-7A53-44BF-8EBE-4ABEB7349399-low.gifFigure 6-18 Timing Diagram for SSP Master (Modes 0/3)