7.3.1 DMD Regulators

DLPA2005 contains three switch-mode power supplies that power the DMD. These rails are VOFS, VBIAS, and VRST. After pulling the PROJ_ON pin high, the DMD is first initialized followed by a power-up of the VOFS line after a small delay of less than 10 ms followed by VBIAS and VRST with an additional delay of 145 ms. The LED driver and STROBE DECODER circuit can only be enabled after all three rails are enabled. There are two power-down sequences, the normal power-down timing initiated after pulling the PROJ_ON pin low, and a fast power-down mode where if any one of the rails encounters a fault such as an output short, all three rails are discharged simultaneously. The detailed power-up and power-down diagrams are shown in Figure 3 and Figure 4.

Figure 3. Power Sequence Normal Shutdown Mode

1. If the FAULT condition happens and its associated interrupt is masked in the Interrupt Mask Register (0Dh), the INTZ does not go low, but all other timing shown in the diagram is unaffected.

Figure 4. Power Sequence Fault Shutdown Mode

7.3.2 RGB Strobe Decoder

DLPA2005 contains RGB color-sequential circuitry that is composed of three NMOS switches, the LED driver, the strobe decoder, and the LED current control. The NMOS switches are connected to the terminals of the external LED package and turn the currents through the LEDs on and off. Package connections are shown in Figure 5 and Figure 9 and corresponding switch map in Table 1.

The LED_SEL[1:0] signals typically receive a rotating code switching from RED to GREEN to BLUE and then back to RED. When the LED_SEL[1:0] input signals select a specific color, the NMOSFETs are controlled based on the color selected, and a 10-bit current control DAC for this color is selected that provides a control current to the RGB LEDs feedback control network.

Figure 5. Switch Connection for a Common-Anode LED Assembly

The switching of the three NMOS switches is controlled such that switches are returned to the open position first before the closed connections are made (break before make). The dead time between opening and closing switches is controlled through the BBM register. Switches that already are in the closed position (and are to remain in the closed state according to the SWCNTRL register) are not opened during the BBM delay time.

Figure 6. BBM Timing (See Register 0Bh in Table 19)

7.3.3 LED Current Control

DLPA2005 provides time-sequential circuitry to drive three LEDs with independent current control. A system based on a common anode LED configuration is shown in Figure 9 and consists of a buck-boost converter, which provides the voltage to drive the LEDs, three switches connected to the cathodes of the LEDs, an RLIM resistor used to sense the LED current, and a current DAC to control the LED current. The voltage measured at the pin V(RLIM_K) is used by the regulator loop.

The STROBE DECODER controls the switch positions as described in the previous section (RGB Strobe Decoder ). With all switches in the open position, the buck-boost output assumes an output voltage of 3.5 V.

For a common-anode RGB LED configuration, the buck-boost output voltage (VLED) assumes a value such that the voltage drop across the sense resistor equals

SPACE

SPACE

when SW4 is closed. The exact value of VLED depends on the current setting and the voltage drop across the LED but is limited to 5.4 V. When the STROBE decoder switches from SW4 to SW5, the buck-boost assumes a new output voltage such that the sense voltage equals:

SPACE

SPACE

and finally when SW6 is selected.

SPACE

SPACE

7.3.4 Maximum Led Currents and Efficiency Considerations

The DLPA2005 comprises a buck-boost power converter to supply the appropriate VLED to the LEDs. The maximum obtainable LED current for a given LED forward voltage are limited by three items:

• The inherent maximum LED current of the PAD2005, i.e. for DAC setting 03FFh.
• The maximum input current of about 4 A.
• The converter efficiency.
• Junction and ambient temperature

In the Figure 2 graph the LED current versus DAC setting is given for several supply voltages (VIN). The load was configured for each supply case such that at the maximum attainable current VOUT max=4.8 V.

For the higher supply voltages VIN>4.5 V the DAC current increases linearly up to the max setting of 3FFh. At that setting the ILED is about 2.5 A. For VIN=2.3 V and VIN=2.7 V the LED current is typically limited to 0.9 A and 1.3 A, respectively. Main reason of this limitation is the maximum input current in combination with the limited converter efficiency. This can be understood by looking at the equation describing the power conversion:

SPACE

For the power converter approaching the maximum input current, the efficiency can roll down significantly. As a result the maximum LED current for VIN=2.3 V and VOUT=4.8 V is about 0.9 A.

The efficiency of the power converter depends on the input supply voltage and the output loading, i.e. output voltage and output current. In the below graph efficiency curves as a function of the LED current are given for several input supply voltages. Again for each of these supply cases the load was controlled such that at maximum output current the output voltage was about 4.8 V.

Figure 7. Measured Typical Power converter efficiency as a function of ILED for several supply voltages (VOUTmax=4.8V for each supply)

Note that in the measurement the output of the buck-boost regulator includes the voltage drop across the sense resistor RLIM, the voltage drop across the internal strobe control switch, and the forward voltage of the LED.

For higher input voltages the power converter runs at an efficiency of 85% or better. For the lower supply voltages because of the boost action, the efficiency quickly rolls down. Refer to section Thermal Considerations for information related to these efficiencies.

7.3.5 Calculating Inductor Peak Current

To properly configure the DLPA2005 device, a 2.2-μH inductor must be connected between pin L1 and pin L2. The peak current for the inductor in steady state operation can be calculated.

Equation 4 shows how to calculate the peak current I₁ in step down mode operation, and Equation 5 shows how to calculate the peak current I₂ in boost mode operation. V_IN1 is the maximum input voltage, V_IN2 is the minimum input voltage, ƒ is the switching frequency (2.25 MHz), and L the inductor value (2.2 μH).

Equation 4.

Equation 5.

The critical current value for selecting the right inductor is the higher value of I₁ and I₂. Also consider that load transients and error conditions may cause higher inductor currents. This needs to be accounted for when selecting an appropriate inductor. Internally the switching current is limited to a maximum of 4 A.

7.3.6 LED Current Accuracy

The LED drive current is controlled by a current DAC (Digital to Analog Converter) and can be set independently for switch SW4, SW5 and SW6. For the DLPA2005, the DAC is trimmed at a current of 2528 mA at code: 0x3FFh, and the step size is 2.47 mA. First order gain-error of the DAC can be neglected, but an offset current error must be taken into account. This offset error differs depending on the used RLIM, and is ±100 mA for the DLPA2005 using a current sense resistor of 39 mΩ.

The max current of the DLPA2005 (SWx_IDAC[9:0] = 0x3FFh) is regulated to 2528 mA. At the lowest setting (SWx_IDAC[9:0] = 0x029h) the current is regulated to 101 mA (DLPA2005). For this current setting (0x028h), the absolute current error results into a large relative error, however this is not a typical operating point.

For best accuracy of the LED current, take the below two considerations into account:

• The LED current setting does not only depend on the accuracy of the RLIM resistor but also strongly depends on the added resistance of pcb traces in the ground route of RLIM and the soldering quality. Due to the low value of the current sense resistor RLIM, any extra introduced resistance of e.g. several milliohms will result in a noticeable different LED current.
• Voltage sensing across RLIM is internally referred to the analog ground, i.e. pin 5 AGND1 and pin 20 GND. To prevent any voltage drop between the ground connection of RLIM and the AGND of the PAD2005, make a star connection of the RLIM ground near pin 5. Take care to make it a low ohmic route that can handle the high LED current. Subsequently, make the ground connection for pin 5 to the system ground low ohmic as well.

Taking the above measures relative to RLIM, the ILED current should align with the calculated value according to:

• Decimal_Code# = (set_current - min_current)/ step_current.
• If needed translate the Decimal_Code# to HEX code before entering in the control software.

7.3.7 Transient Current Limiting

Typically the forward voltages of the green and blue diodes are close to each other (about 3 to 4 V). However, the forward voltage of the red diode is significantly lower (1.8 to 2.5 V). This can lead to a current spike in the red diode when the strobe controller switches from green or blue to red because VLED is initially at a higher voltage than required to drive the RED diode. DLPA2005 provides transient current limiting for each switch to limit the current in the LEDs during the transition. The transient current limit value is controlled through the ILIM[3:0] bits in the IREG register. The same register also contains three bits to select which switch employs the transient current limiting feature. In a typical application, the transient current limit will only apply to the RED diode, and the ILIM[3:0] value will typically be set approximately 10% higher than the DC regulation current. The effect that the transient current limit has on the LED current is shown in Figure 8.

Red LED current without transient current limit. The current overshoots because the buck-boost voltage starts at the (higher) level of the green or blue LED.		LED current with transient current limit.

Figure 8. RED LED Current With and Without Transient Current Limit

Figure 9. LED Driver Block Diagram

7.3.8 1.1-V Regulator (Buck Converter)

The buck converter creates a voltage of 1.1 V, and due to its switching nature, an output ripple with a frequency of approximately 2.25 MHz occurs on its output. This ripple is strongly dependent on the decoupling capacitor at the output in combination with the inductor. The magnitude of the ripple can be calculated with Equation 6.

Equation 6.

The best way to minimize this ripple is to select a capacitor with a very-low ESR.

7.3.9 Measurement System

The measurement system is composed of a 10:1 analog multiplexer (MUX), a programmable-gain amplifier, and a comparator. It works together with the DPP processor to provide:

• White-point correction (WPC) by independently adjusting the RGB LED currents after measuring the brightness of each color with an external light sensor
• A measurement of the:
  • Battery voltage
  • LED forward voltage
  • Exact LED current
  • Temperature as derived by measuring the voltage across an external thermistor

Figure 10 shows a block diagram of the measurement system.

Figure 10. Block Diagram of the Measurement System

7.3.10 Protection Circuits

DLPA2005 has several protection circuits to protect the IC and system from damage due to excessive power consumption, die temperature, or over-voltages. These circuits are described in the following sections.

7.3.10.1 Thermal Warning (HOT) and Thermal Shutdown (TSD)

DLPA2005 continuously monitors the junction temperature and issues a HOT interrupt if temperature exceeds the HOT threshold. If the temperature continues to increase above the thermal shutdown threshold, all rails are disabled and the TSD bit in the INT register is set. After the temperature drops below its threshold, the system recovers and waits for the DPP to resend the DMD_EN bit.

Figure 11. Definition of the Thermal Shutdown and Hot-Die Temperature Warning

7.3.10.2 Low Battery Warning (BAT_LOW) and Undervoltage Lockout (UVLO)

If the battery voltage drops below the BAT_LOW threshold (typically 3 V) the BAT_LOW interrupt is issued, but normal operation continues. After the battery drops below the undervoltage threshold which has a default hardcoded value of 2.3 V (this UVLO voltage can be changed through register 09 h from 2.3 to 4.5 V), the UVLO interrupt is issued, all rails are powered down in sequence, the DMD_EN bit is reset, and the part enters STANDBY mode. The power rails cannot be re-enabled before the input voltage recovers to >2.4 V. To re-enable the rails, the PROJ_ON pin must be toggled. The undervoltage threshold is programmable from 2.3 to 4.5 V in 31 steps.

The UVLO shutdown process will protect the DMD by allowing time for the mirrors to park, then doing a fast discharge of VOFS, VRST, and VBIAS. This protection occurs even in the case of sudden battery removal from the projector, as long as the bulk capacitance on the battery voltage (VINx) keeps this voltage above 2.3 V for as long as needed for VOFS, VRST, and VBIAS to discharge to the required safe levels as shown in the DMD data sheet. VOFS, VRST, and VBIAS discharge times depend on the load capacitance on each regulator. When for instance every supply is decoupled using a capacitor of 0.5 µF, VINx should stay above 2.3 V for at least 100 µs after the battery is suddenly removed. During this time, the mirrors can be placed in a safe position and VOFS, VRST, and VBIAS can be discharged.

NOTE

Capacitive loads should be such that LS_OUT stays above 1.65 V until VOFS, VRST, and VBIAS have discharged to their required safe levels.

1. This time is programmable from 0 to 100 µs

Figure 12. UVLO is Asserted When the Input Supply Drops Below the UVLO Threshold

7.3.10.9 SPI

DLPA2005 provides a 4-wire SPI port that supports high-speed serial data transfers up to 33.3 MHz. Support includes register and data buffer write and read operations. The SPI_CSZ input serves as the active low chip select for the SPI port. The SPI_CSZ input must be forced low in order to write or read registers and data buffers. When SPI_CSZ is forced high, the data at the SPI_DIN input is ignored, and the SPI_DOUT output is forced to a high-impedance state. The SPI_DIN input serves as the serial data input for the port; the SPI_DOUT output serves as the serial data output. The SPI_CLK input serves as the serial data clock for both the input and output data. Data is latched at the SPI_DIN input on the rising edge of SPI_CLK, while data is clocked out of the SPI_DOUT output on the falling edge of SPI_CLK. Figure 13 illustrates the SPI port protocol. Byte 0 is referred to as the command byte, where the most significant bit is the write/not read bit. For the W/nR bit, a 1 indicates a write operation, while a 0 indicates a read operation. The remaining seven bits of the command byte are the register address targeted by the write or read operation. The SPI port supports write and read operations for multiple sequential register addresses through the implementation of an auto-increment mode. As shown in Figure 13, the auto-increment mode is invoked by simply holding the SPI_CSZ input low for multiple data bytes. The register address is automatically incremented after each data byte transferred, starting with the address specified by the command byte. After reaching address 0x7Fh the address pointer jumps back to 0x00h.

Figure 13. SPI Protocol

7.3.11 Password Protected Registers

Register addresses 0x11h through 0x27h can be read-accessed the same way as any other register, but are protected against accidental write operations through the PASSWORD register (address 0x10h). To write to a protected register, follow these steps:

1. Write data 0xBAh to register address 0x10h.
2. Write data 0xBEh to register address 0x10h.

Both writes must be consecutive, that is, there must be no other read or write operation in between sending the two bytes. After the password has been successfully written, registers 0x11h through 0x27h are unlocked and can be write accessed using the regular SPI protocol. They remain unlocked until any byte other than 0xBAh is written to the PASSWORD register or the part is power cycled.

To check if the registers are unlocked, read back the PASSWORD register. If the data returned is 0x00h, the registers are locked. If the PASSWORD register returns 0x01h, the registers are unlocked.

Table 3. Device State as a Function of Control-Pin Status

Table 4. Modes of Operation

Table 5. Register Description

Table 6. Chip Revision Register

Table 7. Enable Register

Table 1. Transient-Current Limit Settings

Table 8. Regulation Current MSB, SW4⁽¹⁾

Table 9. Regulation Current LSB, SW4

Table 10. Regulation Current LSB, SW4 Bit Definitions

Table 11. Regulation Current MSB, SW5⁽¹⁾

Table 12. Regulation Current LSB, SW5

Table 13. Regulation Current LSB, SW5 Bit Definitions

Table 14. Regulation Current MSB, SW6⁽¹⁾

Table 15. Regulation Current LSB, SW6

Table 16. Regulation Current LSB, SW6 Bit Definitions

Table 17. Switch On/Off Control (Direct Mode)

Table 18. AFE (MUX) Control

Table 19. Break Before Make (BBM) Timing

Table 20. Break Before Make (BBM) Timing Bit Definitions⁽¹⁾

Table 21. Interrupt Register

Table 22. Interrupt Register Bit Definitions

Table 23. Interrupt Mask Register

Table 24. Interrupt Mask Register Bit Definitions

Table 25. Timing Register VOFS, VBIAS, VRST, and RESETZ

Table 26. Timing Register VOFS, VBIAS, VRST, and RESETZ Bit Definitions

Table 27. Password Register

Table 28. System Configuration Register

Table 29. System Configuration Register Bit Definitions

Table 30. User EEPROM, BYTE0

Table 31. User EEPROM, BYTE1

Table 32. User EEPROM, BYTE2

Table 33. User EEPROM, BYTE3

Table 34. User EEPROM, BYTE4

Table 35. User EEPROM, BYTE5

Table 36. User EEPROM, BYTE6

Table 37. User EEPROM, BYTE7