SBAS368D May   2006  – December 2016 DDC264

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Dual Switched Integrator: Basic Integration Cycle
      2. 8.3.2 Integration Capacitors
      3. 8.3.3 Voltage Reference
      4. 8.3.4 Serial Data Output and Control Interface
        1. 8.3.4.1 System and Data Clocks (CLK and DCLK)
        2. 8.3.4.2 CONV: Setting the Integration Time
        3. 8.3.4.3 Data Valid (DVALID)
        4. 8.3.4.4 Data Format
        5. 8.3.4.5 Data Retrieval
          1. 8.3.4.5.1 Cascading Multiple Converters
          2. 8.3.4.5.2 Retrieval Before CONV Toggles
          3. 8.3.4.5.3 Retrieval After CONV Toggles
          4. 8.3.4.5.4 Retrieval Before and After CONV Toggles
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 Reset (RESET)
      2. 8.5.2 Configuration Register — Read and Write Operations
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Connection
        2. 9.2.2.2 Selecting Integration Time, Device Clock, and Range
        3. 9.2.2.3 Voltage Reference
        4. 9.2.2.4 Reading the Measurement
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Power-Up Sequencing
    2. 10.2 Power Supplies and Grounding
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Shielding Analog Signal Paths
      2. 11.1.2 Power Supply Routing
      3. 11.1.3 Reference Routing
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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6 Pin Configuration and Functions

ZAW Package
100-Pin NFBGA
Top View
DDC264 po_bas368.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
AGND A8, B8, C7, C8, D7, E7, F7, F8, H8, J8. K8 Analog Analog ground
AVDD F9, G8, G9, H9, J9, K9 Analog Analog power supply, 5-V nominal
CLK F10 Digital input Master clock input
CLK_CFG A9 Digital input Configuration register clock input
CONV K10 Digital input Conversion control input: 0 = integrate on side B; 1 = integrate on side A
DCLK C10 Digital input Serial data clock input
DGND D9, E9, H10, J10 Digital Digital ground
DIN B10 Digital input Serial data input
DIN_CFG B9 Digital input Configuration register data input
DOUT A10 Digital output Serial data output
DVALID G10 Digital output Data valid output, active low
DVDD D10, E10 Digital Digital power supply, 3.3-V nominal
IN1-IN64 Rows 1-6, A7, B7, J7, K7 Analog input Analog inputs for channels 1 to 64
QGND G7, H7 Analog Quiet analog ground; see the guidelines described in Layout
RESET C9 Digital input Digital reset, active low
VREF D8, E8 Analog input External voltage reference input, 4.096-V nominal