SBAS368D May   2006  – December 2016 DDC264


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Dual Switched Integrator: Basic Integration Cycle
      2. 8.3.2 Integration Capacitors
      3. 8.3.3 Voltage Reference
      4. 8.3.4 Serial Data Output and Control Interface
        1. System and Data Clocks (CLK and DCLK)
        2. CONV: Setting the Integration Time
        3. Data Valid (DVALID)
        4. Data Format
        5. Data Retrieval
          1. Cascading Multiple Converters
          2. Retrieval Before CONV Toggles
          3. Retrieval After CONV Toggles
          4. Retrieval Before and After CONV Toggles
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 Reset (RESET)
      2. 8.5.2 Configuration Register — Read and Write Operations
    6. 8.6 Register Maps
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. Input Connection
        2. Selecting Integration Time, Device Clock, and Range
        3. Voltage Reference
        4. Reading the Measurement
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Power-Up Sequencing
    2. 10.2 Power Supplies and Grounding
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Shielding Analog Signal Paths
      2. 11.1.2 Power Supply Routing
      3. 11.1.3 Reference Routing
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information


机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)


  • Single-Chip Solution to Directly Measure 64 Low-Level Currents
  • Proven High-Precision, True Integrating Architecture With 100% Charge Collection
  • Easy Upgrade for Existing DDC Family Applications
  • Very Low Power: 3 mW/channel
  • Extremely Linear:
    INL = ±0.025% of Reading ±1 ppm of FSR
  • Low Noise: 6.3 ppm of FSR
  • Adjustable Full-Scale Range
  • Adjustable Speed
    • Data Rates up to 6 kSPS With 20-bit Performance
    • Integration Times as low as 160 µs
  • Daisy-Chainable Serial Interface
  • In-Package Bypass Capacitors Simplify PCB Design


  • CT Scanner DAS
  • Photodiode Sensors
  • X-Ray Detection Systems


    Simplified Schematic

    DDC264 simplified_schematic_SBAS368.gif
    Protected by US Patent #5841310


The DDC264 is a 20-bit, 64-channel, current-input analog-to-digital (A/D) converter. It combines both current-to-voltage and A/D conversion so that 64 separate low-level current output devices, such as photodiodes, can be directly connected to its inputs and digitized.

For each of the 64 inputs, the DDC264 uses the proven dual switched integrator front-end. This configuration allows for continuous current integration: while one integrator is being digitized by the onboard A/D converter, the other is integrating the input current. This architecture provides both a very stable offset and a loss-less collection of the input current. Adjustable integration times range from 160 µs to 1 s, allowing currents from fAs to µAs to be continuously measured with outstanding precision.

The DDC264 has a serial interface designed for daisy-chaining in multi-device systems. Simply connect the output of one device to the input of the next to create the chain. Common clocking feeds all the devices in the chain so that the digital overhead in a multi-DDC264 system is minimal.

The DDC264 uses a 5-V analog supply and a 2.7-V to 3.6-V digital supply. Bypass capacitors within the DDC264 package help minimize the external component requirements. Operating over the temperature range of 0°C to 70°C, the DDC264
100-pin NFBGA package is offered in two versions: the DDC264C for low-power applications, and the DDC264CK when higher speeds are required.

Device Information(1)

DDC264 NFBGA (100) 9.00 mm × 9.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Revision History

Changes from C Revision (July 2011) to D Revision

  • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information sectionGo
  • Moved AVDD and DVDD rows to Recommended Operating Conditions tableGo
  • Moved Dynamic Characteristics rows to Recommended Operating Conditions table Go
  • Deleted Voltage row from Electrical Characteristics table Go
  • Changed 1.65 mA to 825 µA in Voltage Reference sectionGo
  • Changed 680 µA to 340 µA in Voltage Reference sectionGo
  • Changed 64 to 128 in the formula in Reading the Measurement sectionGo
  • Changed high-impedance to low-impedance in Shielding Analog Signal Paths sectionGo

Changes from B Revision (January, 2011) to C Revision

  • Updated NOISE vs CSENSOR table; revised values for Range 0 performance in fC and ElectronsGo

Changes from A Revision (January, 2011) to B Revision

  • Changed second paragraph of Basic Integration Cycle section to correct CONV timing description errorGo