ZHCSFZ2 February   2017 DAC8775

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: Write and Readback Mode
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Current Output Stage
      2. 8.3.2  Voltage Output Stage
      3. 8.3.3  Buck-Boost Converter
        1. 8.3.3.1 Buck-Boost Converters Outputs
        2. 8.3.3.2 Selecting and Enabling Buck-Boost Converters
        3. 8.3.3.3 Configurable Clamp Feature and Current Output Settling Time
          1. 8.3.3.3.1 Default Mode - CCLP[1:0] = "00" - Current Output Only
          2. 8.3.3.3.2 Fixed Clamp Mode - CCLP[1:0] = "01" - Current and Voltage Output
          3. 8.3.3.3.3 Auto Learn Mode - CCLP[1:0] = "10" - Current Output Only
          4. 8.3.3.3.4 High Side Clamp (HSCLMP)
        4. 8.3.3.4 Buck-Boost Converters and Open Circuit Current Output
      4. 8.3.4  Analog Power Supply
      5. 8.3.5  Digital Power Supply
      6. 8.3.6  Internal Reference
      7. 8.3.7  Power-On-Reset
      8. 8.3.8  ALARM Pin
      9. 8.3.9  Power GOOD Bits
      10. 8.3.10 Status Register
      11. 8.3.11 Status Mask
      12. 8.3.12 Alarm Action
      13. 8.3.13 Watchdog Timer
      14. 8.3.14 Programmable Slew Rate
      15. 8.3.15 HART Interface
    4. 8.4 Device Functional Modes
      1. 8.4.1 Serial Peripheral Interface (SPI)
        1. 8.4.1.1 Stand-Alone Operation
        2. 8.4.1.2 Daisy-Chain Operation
      2. 8.4.2 SPI Shift Register
      3. 8.4.3 Write Operation
      4. 8.4.4 Read Operation
      5. 8.4.5 Updating the DAC Outputs and LDAC Pin
        1. 8.4.5.1 Asynchronous Mode
        2. 8.4.5.2 Synchronous Mode
      6. 8.4.6 Hardware RESET Pin
      7. 8.4.7 Hardware CLR Pin
      8. 8.4.8 Frame Error Checking
      9. 8.4.9 DAC Data Calibration
        1. 8.4.9.1 DAC Data Gain and Offset Calibration Registers
    5. 8.5 Register Maps
      1. 8.5.1 DAC8775 Commands
      2. 8.5.2 Register Maps and Bit Functions
        1. 8.5.2.1  No Operation Register (address = 0x00) [reset = 0x0000]
        2. 8.5.2.2  Reset Register (address = 0x01) [reset = 0x0000]
        3. 8.5.2.3  Reset Config Register (address = 0x02) [reset = 0x0000]
        4. 8.5.2.4  Select DAC Register (address = 0x03) [reset = 0x0000]
        5. 8.5.2.5  Configuration DAC Register (address = 0x04) [reset = 0x0000]
        6. 8.5.2.6  DAC Data Register (address = 0x05) [reset = 0x0000]
        7. 8.5.2.7  Select Buck-Boost Converter Register (address = 0x06) [reset = 0x0000]
        8. 8.5.2.8  Configuration Buck-Boost Register (address = 0x07) [reset = 0x0000]
        9. 8.5.2.9  DAC Channel Calibration Enable Register (address = 0x08) [reset = 0x0000]
        10. 8.5.2.10 DAC Channel Gain Calibration Register (address = 0x09) [reset = 0x0000]
        11. 8.5.2.11 DAC Channel Offset Calibration Register (address = 0x0A) [reset = 0x0000]
        12. 8.5.2.12 Status Register (address = 0x0B) [reset = 0x1000]
        13. 8.5.2.13 Status Mask Register (address = 0x0C) [reset = 0x0000]
        14. 8.5.2.14 Alarm Action Register (address = 0x0D) [reset = 0x0000]
        15. 8.5.2.15 User Alarm Code Register (address = 0x0E) [reset = 0x0000]
        16. 8.5.2.16 Reserved Register (address = 0x0F) [reset = N/A]
        17. 8.5.2.17 Write Watchdog Timer Register (address = 0x10) [reset = 0x0000]
        18. 8.5.2.18 Device ID Register (address = 0x11) [reset = 0x0000]
        19. 8.5.2.19 Reserved Register (address 0x12 - 0xFF) [reset = N/A]
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Buck-Boost Converter External Component Selection
      2. 9.1.2 Voltage and Current Ouputs on a Shared Terminal
      3. 9.1.3 Optimizing Current Output Settling time with Auto learn Mode
      4. 9.1.4 Protection for Industrial Transients
      5. 9.1.5 Implementing HART with DAC8775
    2. 9.2 Typical Application
      1. 9.2.1 1W Power Dissipation, Quad Channel, EMC and EMI Protected Analog Output Module with Adaptive Power Management
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档　
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Input voltage PVDD_x/AVDD to PBKG -0.3 40 V
PVSS_x/REFGND/DCDC_AGND_x/DAC_AGND_x to PBKG -0.3 0.3
VPOS_IN_x to VNEG_IN_x -0.3 40
VPOS_IN_x to PBKG -0.3 33
VNEG_IN_x to PBKG -20 0.3
VSENSEN_x to PBKG VNEG_IN_x VPOS_IN_x
VSENSEP_x to PBKG VNEG_IN_x VPOS_IN_x
DVDD to PBKG -0.3 6
REFOUT/REFIN to PBKG -0.3 6
Digital input voltage to PBKG -0.3 DVDD+0.3
Output voltage VOUT_x to PBKG VNEG_IN_x VPOS_IN_x V
IOUT_x to PBKG VNEG_IN_x VPOS_IN_x
SDO, ALARM to PBKG -0.3 DVDD+0.3
Input current Current into any digital input pin -10 10 mA
Power dissipation (TJmax – TA)/θJA W
Operating junction temperature, TJ -40 150 °C
Junction temperature range, TJmax 150
Storage temperature, Tstg -65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
POWER SUPPLY
PVDD_x/AVDD_x to PBKG/PVSS_x(1) Positive supply voltage to ground range 12 36 V
VPOS_IN_x to PBKG(1) Positive supply voltage to ground range 12 33 V
VNEG_IN_x to PBKG(1) Negative supply voltage to substrate for current output mode -18 0 V
Negative supply voltage to substrate for voltage output mode -18 -5 V
VPOS_IN_x to VNEG_IN_x(1) 12 36 V
VSENSEN_x to PBKG The minimum headroom spec for voltage output stage must be met -7 7 V
DVDD to PBKG Digital supply voltage to substrate 2.7 5.5 V
DIGITAL INPUTS
VIH Input high voltage 2 V
VIL Input low voltage 0.6 V
REFERENCE INPUT
REFIN to PBKG Reference input to substrate 4.95 5.05 V
TEMPERATURE RANGE
TA Operating temperature -40 125 °C
(1) The minimum headroom spec for voltage output stage and the compliance voltage for current output stage should be met. When Buck-Boost converter is enabled VPOS_IN_x/VNEG_IN_x are generated internally to meet headroom and compliance specs. When Buck-Boost converter is disabled VPOS_IN_x, AVDD, and PVDD must be tied together.

7.4 Thermal Information

THERMAL METRIC(1) DAC8775 UNIT
RWF (VQFN)
72 PINS
RθJA Junction-to-ambient thermal resistance 21.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 3.3 °C/W
RθJB Junction-to-board thermal resistance 1.9 °C/W
ΨJT Junction-to-top characterization parameter 0.1 °C/W
ΨJB Junction-to-board characterization parameter 1.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.2 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

AVDD/PVDD_x/VPOS_IN_x = +15 V, VNEG_IN_x = -15 V, VSENSEN_x = PBKG = PVSS_x = 0 V, External DVDD = 2.7 V. VOUT : RL = 1 kΩ, CL = 200 pF, IOUT : RL = 250 Ω; all specifications -40℃ to +125℃, unless otherwise noted. REFIN= +5 V external;, Buck-Boost Converter disabled unless otherwise stated
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT OUTPUT
IOUT Output Current Ranges 0 24 mA
0 20 mA
3.5 23.5 mA
-24 24 mA
4 20 mA
Accuracy
Resolution 16 Bits
INL Relative Accuracy(1) All ranges except bipolar range -12 12 LSB
Bipolar range only -16 16 LSB
DNL Differential Nonlinearity(1) Ensured monotonic -1 1 LSB
TUE Total Unadjusted Error(1) -40℃ to +125℃ -0.14 0.14 %FSR
-40℃ to +125℃, 4 to 20 mA -0.4 0.4 %FSR
TA = +25℃, 4 to 20 mA -0.2 0.2 %FSR
TA = +25°C -0.12 0.12 %FSR
OE Offset Error(1) -40℃ to +125℃ -0.1 0.1 %FSR
TA = +25°C -0.05 0.05 %FSR
OE-TC Offset Error Temperature Coefficient -40℃ to +125℃ 4 ppm FSR/ºC
ZCE Zero Code Error -40℃ to +125℃, 0x0000h into DAC -15 15 uA
-40℃ to +125℃, 0x0000h into DAC, 4 to 20 mA -18 18 uA
TA = 25℃, 0x0000h into DAC 1.2 m%FSR
TA = 25℃, 0x0000h into DAC, 4 to 20 mA 1.8 m%FSR
ZCE-TC Zero Code Error Temperature Coefficient 0x0000h into DAC, -40℃ to +125℃ 4 ppm/ºC
GE Gain Error(2) -40℃ to +125℃ -0.125 0.125 %FSR
-40℃ to +125℃, 4 to 20 mA -0.25 0.25 %FSR
TA = +25℃, 4 to 20 mA -0.2 0.2 %FSR
TA = +25°C -0.12 0.12 %FSR
GE-TC Gain Error Temperature Coefficient -40℃ to +125℃ 3 ppm FSR/ºC
PFSE Positive Full Scale Error 0xFFFFh into DAC, -40℃ to +125℃ -0.125 0.125 %FSR
0xFFFFh into DAC, -40℃ to +125℃, 4 to 20 mA -0.25 0.25 %FSR
0xFFFFh into DAC, TA = 25℃ 0.016 %FSR
0xFFFFh into DAC, TA = 25℃, 4 to 20 mA 0.024 %FSR
NFSE Negative Full Scale Error 0x0000h into DAC, Bipolar range only, -40℃ to +125℃ -0.125 0.125 %FSR
0x0000h into DAC, Bipolar range only, TA = 25℃ 0.02 %FSR
PFSE-TC Positive Full Scale Error Temperature Coefficient 5 ppm FSR/ºC
NFSE-TC Negative Full Scale Error Temperature Coefficient Bipolar range only 5 ppm FSR/ºC
BPZE Bipolar Zero Error Bipolar range only, 0x8000h into DAC -40℃ to +125℃ -0.05 0.05 %FSR
Bipolar range only, 0x8000h into DAC, TA = +25°C -0.02 0.02
BPZE-TC Bipolar Zero Error Temperature Coefficient 0x8000h into DAC,-40℃ to +125℃ 4 ppm/ºC
VCL Compliance Voltage Output = 24 mA VPOS_IN_x-3 V
Output = ±24 mA |VNEG_IN_x|+3 VPOS_IN_x-3 V
RL Resistive Load All except ±24 mA range 1.2 KΩ
±24 mA range 0.625
DC-PSRR DC Power Supply Rejection Ratio Code = 0x8000, 20 mA range 0.1 µA/V
ZO Output Impedance Code = 0x8000 10 MΩ
IOLEAK Output Current Leakage Iout is disabled or in power-down 1 nA
HART INTERFACE
VHART-IN HART Input 400 500 600 mVpp
Corresponding Output HART In = 500 mVpp 1.2 KHz 1 mApp
VOLTAGE OUTPUT
VOUT Voltage Output Ranges (normal mode) 0 5 V
0 10 V
-5 5 V
-10 10 V
Voltage Output Ranges (Overrange mode) 0 6 V
0 12 V
-6 6 V
-12 12 V
Accuracy
Resolution 16 Bits
INL Relative Accuracy, INL(1) -12 12 LSB
DNL Differential Nonlinearity, DNL(1) Ensured monotonic -1 1 LSB
TUE Total Unadjusted Error, TUE(1) -40℃ to +125℃, VOUT unloaded -0.1 ±0.05 0.1 %FSR
TA = +25°C, VOUT unloaded -0.075 0.075 %FSR
ZCE Zero Code Error(5) Unipolar ranges only, VOUT unloaded, -40℃ to +125℃ -2.5 2.5 mV
Unipolar ranges only, VOUT unloaded, TA = 25℃ 0.14 mV
ZCE-TC Zero Code Error Temperature Coefficient Unipolar ranges only, -40℃ to +125℃ 2 ppm FSR/ºC
BPZE Bipolar Zero Error Bipolar range only, 0x8000h into DAC -40℃ to +125℃, VOUT unloaded -0.03 0.03 %FSR
Bipolar range only, 0x8000h into DAC, TA = +25°C, VOUT unloaded -0.025 0.025 %FSR
BPZE-TC Bipolar Zero Error Temperature Coefficient Bipolar range only, 0x8000h into DAC, -40℃ to +125℃, VOUT unloaded 1 ppm FSR/ºC
GE Gain Error(1) -40℃ to +125℃, VOUT unloaded -0.1 0.1 %FSR
TA = +25°C, VOUT unloaded -0.07 0.07 %FSR
GE-TC Gain Error Temperature Coefficient -40℃ to +125℃ 3 ppm FSR/ºC
PFSE Positive Full Scale Error 0xFFFFh into DAC, -40℃ to +125℃, VOUT unloaded -0.1 0.1 %FSR
0xFFFFh into DAC, TA = 25℃, VOUT unloaded 0.03 %FSR
NFSE Negative Full Scale Error(5) Bipolar ranges only, 0x0000h into DAC, -40℃ to +125℃, VOUT unloaded -0.06 0.06 %FSR
Bipolar ranges only, 0x0000h into DAC, TA = 25℃, VOUT unloaded 0.002 %FSR
PFSE-TC Positive Full Scale Error Temperature Coefficient VOUT unloaded, -40℃ to +125℃ 2 ppm FSR/ºC
NFSE-TC Negative Full Scale Error Temperature Coefficient VOUT unloaded, -40℃ to +125℃ 2 ppm FSR/ºC
Headroom Output unloaded, VPOS_IN_x with respect to VOUT_x, 0xFFFFh into DAC, No load 0.5 V
Output unloaded, VPOS_IN_x with respect to VOUT_x, 0xFFFFh into DAC, 1 kΩ load 3 V
Footroom Bipolar, ranges only, VNEG_IN_x with respect to VOUT_x, 0x0000h into DAC 3 V
Unipolar ranges only, VNEG_IN_x with respect to VOUT_x, 0x0000h into DAC 5 V
Short-Circuit Current SCLIM[1:0] = "00" (see register map) 17 23 mA
SCLIM[1:0] = "01" (see register map) 8 11 mA
SCLIM[1:0] = "10" (see register map) 22 28 mA
SCLIM[1:0] = "11" (see register map) 26 34 mA
RL Load 1 kΩ
CL Capacitive Load Stability RL = Open 20 nF
RL = 1 kΩ 20 nF
RL = 1 kΩ with External compensation capacitor (150 pF) connected 1 µF
ZO DC Output Impedance Voltage output enabled, VOUT = Mid Scale, UP10V range 0.01 Ω
Voltage output disabled (POC = '1') 50 MΩ
Voltage output disabled (POC = '0') 30 kΩ
ILEAK Output Leakage (VOUT_x Pin) Voltage output disabled (POC = '1') 1 nA
DC-PSRR DC Power Supply Rejection Ratio No output load 10 µV/V
VSENSEP Impedance VOUT enabled Mid-Scale UP10 240 kΩ
VSENSEN Impedance VOUT enabled Mid-Scale UP10 120 kΩ
EXTERNAL REFERENCE INPUT
IREF External Reference Current VOUT = Full scale, BP12V range, per channel 0.35 mA
Reference Input Capacitance 100 pF
INTERNAL REFERENCE OUTPUT
VREF Reference Output TA = 25°C 4.99 5.01 V
VREF-TC Reference TC TA = -40℃ to +125℃ -13 13 ppm/°C
TA = -25℃ to +125℃ -10 10 ppm/°C
TUE DAC Voltage Output Total Unadjusted Error(1) -40°C to +125°C, VOUT_x unloaded, Internal reference enabled 0.2 %FSR
DAC Current Output Total Unadjusted Error(1) -40°C to +125°C, Internal reference enabled 0.2 %FSR
-40°C to +125°C, Internal reference enabled, 4 mA to 20 mA range 0.5 %FSR
Output Noise (0.1 Hz to 10 Hz) TA = 25°C 13 µV p-p
Noise Spectral Density At 10 kHz, At 25°C 200 nV/sqrtHz
CL Capacitive Load 600 nF
IL Load Current ±5 mA
Short Circuit Current Ref-Out shorted to PBKG 20 mA
Load Regulation Sourcing and Sinking, TA = +25°C 5 µV/mA
Line Regulation TA = +25°C 2 uV/V
BUCK BOOST CONVERTER
RON Switch On Resistanvce TA = +25°C 3 Ω
ILEAK Switch Leakage Current TA = +25°C 20 nA
L Inductor Between LP_x and LN_x 100 µH
ILMAX Peak Inductor Current TA = +25°C, PVDD = AVDD = 36 V, Buck-Boost Converter enabled 0.5 A
VO Output Voltage VPOS_IN_x minimum 4 V
VPOS_IN_x maximum 32 V
VO Output Voltage VNEG_IN_x minimum -18 V
VNEG_IN_x maximum -5 V
CL Load Capacitor VPOS_IN_x and VNEG_IN_x 10 µF
Start Up Time After enabling VPOS_IN_x and VNEG_IN_x with 10 µF load capacitor on these pins 3 ms
DVDD LDO
VO Output Voltage 5 V
ILOAD Load Current 10 mA
CL Load Capacitor 0.2 nF
THERMAL ALARM
Trip Point 150 °C
Hysteresis 15 °C
DIGITAL INPUTS
Hysteresis Voltage 0.4 V
Input Current -5 5 µA
Input Current (DVDD_EN) -10 10 µA
Pin Capacitance Per pin 10 pF
DIGITAL OUTPUTS
SDO
VOL Output Low Voltage Sinking 200 µA 0.4 V
VOH Output High Voltage Sourcing 200 µA DVDD-0.5 V
ILEAK High Impedance Leakage -5 5 µA
High Impedance Output Capacitance 10 pF
ALARM
VOL Output Low Voltage At 2.5 mA 0.4 V
ILEAK High Impedance Leakage 50 µA
High Impedance Output Capacitance 10 pF
POWER REQUIREMENTS
IAVDD+IPVDD Current Flowing into AVDD and PVDD All Buck-Boost converter positive output enabled, IOUT_x mode operation, All IOUT channels enabled, 0 mA, PVDD = AVDD = 12 V, Internal reference, VNEG_IN_x = 0 V 5 mA
All IOUT Active, 0 mA, 0 to 24 mA range, VNEG_IN_x = 0 V 3.5 5 mA
IPVDD_x Current Flowing into PVDD Buck-Boost converter enabled, Peak current 0.5 A
Buck-Boost converter disabled 0.1 mA
IDVDD Current Flowing into DVDD All digital pins at DVDD, DVDD = 5.5 V 1.8 mA
IVPOS_IN_x Current Flowing into VPOS_IN_x IOUT active, 0 mA, 0 to 24 mA range 1.2 mA
VOUT active, No load, 0  to 10 V range, Mid scale code 3 mA
IVNEG_IN_x Current Flowing into VNEG_IN_x IOUT active, 0 mA, ±24 mA range 1.2 mA
VOUT active, No load, 0 to 10 V range, Mid scale code 3 mA
PDISS Power Dissipation (PVDD+AVDD) All Buck-Boost converter positive output enabled, IOUT_x mode operation, All IOUT channels enabled, Rload = 1 Ω, 24 mA, PVDD = AVDD = 12 V, Internal reference, VNEG_IN_x = 0 V 0.86 1.1 W
IVSENSEP Current Flowing into VSENSEP VOUT disabled 40 nA
IVSENSEN Current Flowing into VSENSEN VOUT disabled 20 nA
DYNAMIC PERFORMANCE
Voltage Output
Tsett Output Voltage Settling Time 0 to10 V, to ±0.03% FSR RL = 1K||CL = 200 pF 15 µs
0 to 5 V, to ±0.03% FSR RL = 1K||CL = 200 pF 10 µs
-5 to 5 V, to ±0.03% FSR RL = 1K||CL = 200 pF 15 µs
-10 to 10 V, to ±0.03% FSR RL = 1K||CL = 200 pF 30 µs
Output Voltage Ripple Buck-Boost converter enabled, 50 KHz, 20dB/decade filter on VPOS_IN_x 2 mVpp
SR Slew Rate RL = 1K||CL = 200 pF 1 V/µs
Power-On Glitch Magnitude(2) 0.1 V
Power-off Glitch Magnitude(3) 0.8 V
Channel to Channel DC Crosstalk Full scale swing on adjacent channel 2 m%FSR
Code-to-Code Glitch 0.15 µV-sec
Digital Feedthrough 1 nV-sec
Output Noise (0.1 Hz to 10 Hz bandwidth) UP10V, Mid scale 0.1 LSB p-p
Output Noise (100 kHz bandwidth) UP10V, Mid scale 200 µVrms
Output Noise Spectral Density BP20V Measured at 10 kHz, Mid scale 200 nV/sqrtHz
AC-PSRR AC Power Supply Rejection Ratio 200 mV 50/60Hz Sine wave superimposed on power supply voltage. (AC analysis) -75 dB
Current Output
Tsett Output Current Settling Time 24 mA Step, to 0.1% FSR, no L 10 µs
24 mA Step, to 0.1% FSR , L = 1 mH, CL = 22 nF 50 µs
Output Current Ripple Buck-Boost converter enabled, 50 KHz, 20dB/decade filter on VPOS_IN_x 8 µApp
L Inductive Load(4) 50 mH
AC-PSRR AC Power Supply Rejection Ratio 200 mV 50/60Hz Sine wave superimposed on power supply voltage. -75 dB
(1) For current output all ranges except ±24 mA, low code of 256d and a high code of 65535d are used, for ±24 mA range low code of 0d and a high code of 65535d. For voltage output, low code of 256d and a high code of 65535d are used
(2) No load, DVDD supply ramps up before VPOS_IN_x,and VNEG_IN_x, ramp rate of VPOS_IN_x,and VNEG_IN_x limited to 18 V/msec
(3) Vout disabled, no load, ramp rate of VPOS_IN_x,and VNEG_IN_x limited to 18 V/msec
(4) 680 nF is required at IOUT pin for 50 mH pure inductor load.
(5) DAC code at 0d, this error includes offset error of the DAC since the DAC is linear between 0d to 65535d

7.6 Timing Requirements: Write and Readback Mode

At TA = –40°C to +125°C and DVDD = +2.7 V to +5.5 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN MAX UNIT
fSCLK Max clock frequency 25 MHz
t1 SCLK cycle time 40 ns
t2 SCLK high time 18 ns
t3 SCLK low time 18 ns
t4 SYNC falling edge to SCLK falling edge setup time 15 ns
t5 24th/32nd SCLK falling edge to SYNC rising edge 13 ns
t6 SYNC high time 40 ns
t7 Data setup time 8 ns
t8 Data hold time 5 ns
t9 SYNC rising edge to LDAC falling edge 33 ns
t10 LDAC pulse width low 10 ns
t11 LDAC falling edge to DAC output response time 50 ns
t12 DAC output settling time See Electrical Characteristics µs
t13 CLR high time 10 ns
t14 CLR activation time 50 ns
t15 SCLK rising edge to SDO valid 14 ns
t16 SYNC rising edge to DAC output response time 50 ns
t17 LDAC falling edge to SYNC rising edge 100 ns
t18 RESET pulse width 10 ns
t19 SYNC rising edge to CLR falling/rising edge 60 ns
DAC8775 WriteTiming_SLVSBY7_DAC8775.gif Figure 1. Write Mode Timing
DAC8775 ReadTiming_SLVSBY7_DAC8775.gif Figure 2. Readback Mode Timing

7.7 Typical Characteristics

AVDD/PVDD_x/VPOS_IN_x = +15 V, VNEG_IN_x = –15 V, PBKG = PVSS_x = 0 V, External DVDD = 5 V, VOUT disabled, IOUT RL = 250 Ω, TA = 25℃, REFIN = +5 V external, Buck-Boost Converter disabled, unless otherwise stated.
DAC8775 C036_IOUT_INL_v_code.png
Figure 3. IOUT Linearity Error vs Digital Input Code
DAC8775 C037_IOUT_TUE_v_code.png
Figure 5. IOUT Total Unadjusted Error vs Digital Input Code
DAC8775 C039_IOUT_DNL_v_temp.png
Figure 7. IOUT Differential Linearity Error vs Temperature
DAC8775 C035_IOUT_DNL_v_code.png
Figure 4. IOUT Differential Linearity Error vs Digital Input Code
DAC8775 C040_IOUT_INL_v_temp.png
Figure 6. IOUT Linearity Error vs Temperature
DAC8775 C041_IOUT_TUE_v_temp.png
Figure 8. IOUT Total Unadjusted Error vs Temperature
AVDD/PVDD_x/VPOS_IN_x = +15 V, VNEG_IN_x = –15 V, PBKG = PVSS_x = 0 V, External DVDD = 5 V VOUT disabled, IOUT RL = 250 Ω, TA = 25℃, REFIN= +5 V external, Buck-Boost Converter disabled, unless otherwise stated.
DAC8775 C046_IOUT_OE_v_temp.png
Figure 9. IOUT Offset Error vs Temperature
DAC8775 C045_IOUT_ZCE_v_temp.png
Figure 11. IOUT Zero Code Error vs Temperature
DAC8775 C038_IOUT_BPZ_v_temp.png
Figure 13. IOUT Bipolar Zero Error vs Temperature
DAC8775 C043_IOUT_GE_v_temp.png
Figure 10. IOUT Gain Error vs Temperature
DAC8775 C042_IOUT_FSE_v_temp.png
Figure 12. IOUT Full Scale Error vs Temperature
DAC8775 C044_IOUT_MFSE_v_temp.png
Figure 14. IOUT Negative Full Scale Error vs Temperature
AVDD/PVDD_x = VPOS_IN_x , VNEG_IN_x = PBKG = PVSS_x = 0 V, External DVDD = 5 V VOUT disabled, IOUT RL = 250 Ω, TA = 25℃, REFIN = +5 V external, Buck-Boost Converter disabled, unless otherwise stated.
DAC8775 C048_IOUT_INL_v_PS.png
Figure 15. IOUT Linearity Error vs Power Supplies
DAC8775 C051_BP24mA_INL_v_PS.png
|VPOS_IN_x| = |VNEG_IN_x|
Figure 17. IOUT Linearity Error vs Power Supplies
DAC8775 C049_IOUT_TUE_v_PS.png
Figure 19. IOUT Total Unadjusted Error vs Power Supplies
DAC8775 C047_IOUT_DNL_v_PS.png
Figure 16. IOUT Differential Linearity Error vs Power Supplies
DAC8775 C050_BP24mA_DNL_v_PS.png
|VPOS_IN_x| = |VNEG_IN_x|
Figure 18. IOUT Differential Linearity Error vs Power Supplies
DAC8775 C052_BP24mA_TUE_v_PS.png
|VPOS_IN_x| = |VNEG_IN_x|
Figure 20. IOUT Total Unadjusted Error vs Power Supplies
AVDD/PVDD_x/VPOS_IN_x = +15 V, VNEG_IN_x = –15 V, PBKG = PVSS_x = 0 V, External DVDD = 5 V VOUT disabled, IOUT RL = 250 Ω, TA = 25℃, REFIN = +5 V external, Buck-Boost Converter disabled, unless otherwise stated.
DAC8775 C064_IOUT_VPOS_IDD_v_code.png
±24 mA Range
Figure 21. IOUT Power Supply Current vs Digital Input Code
DAC8775 C066_IOUT_VPOS_IDD_v_PS.png
|VPOS_IN_x| = |VNEG_IN_x|, ±24 mA Range, Mid Scale Code
Figure 23. IOUT Power Supply Current vs Power Supplies Voltages
DAC8775 C065_IOUT_VPOS_IDD_v_temp.png
±24 mA Range, Mid Scale Code
Figure 22. IOUT Power Supply Current vs Temperature
AVDD/PVDD_x/VPOS_IN_x = +15 V, VNEG_IN_x = –15 V, PBKG = PVSS_x = 0 V, External DVDD = 5 V VOUT disabled, IOUT RL = 250 Ω, TA = 25℃, REFIN = +5 V external, Buck-Boost Converter disabled, unless otherwise stated.
DAC8775 C053_24mA_rising_settling.png
0-24 mA Range
Figure 24. IOUT Full-Scale Settling Time, Rising Edge
DAC8775 C054_24mA_falling_settling.png
0-24 mA Range
Figure 26. IOUT Full-Scale Settling Time, Falling Edge
DAC8775 C057_IOUT_7FFF_8000.png
0-24 mA Range, 7FFFh - 8000h
Figure 28. IOUT Glitch Impulse, Rising Edge, 1LSB Step
DAC8775 C056_BP24mA_rising_settling.png
AVDD/PVDD_x/VPOS_IN_x = +18 V, VNEG_IN_x = –18 V,
IOUT RL = 625 Ω
Figure 25. IOUT Full-Scale Settling Time, Rising Edge
DAC8775 C055_BP24mA_falling_settling.png
AVDD/PVDD_x/VPOS_IN_x = +18 V, VNEG_IN_x = –18 V,
IOUT RL = 625 Ω
Figure 27. IOUT Full-Scale Settling Time, Falling Edge
DAC8775 C058_IOUT_8000_7FFF.png
0-24 mA Range, 8000h - 7FFFh
Figure 29. IOUT Glitch Impulse, Falling Edge, 1LSB Step
AVDD/PVDD_x/VPOS_IN_x = +15 V, VNEG_IN_x = –15 V, PBKG = PVSS_x = 0 V, External DVDD = 5 V VOUT disabled, IOUT RL = 250 Ω, TA = 25℃, REFIN = +5 V external, Buck-Boost Converter disabled, unless otherwise stated.
DAC8775 C058_IOUT_Power_ON_Glitch.png
Figure 30. IOUT Power-On Glitch
DAC8775 C060_IOUT_pk_noise.png
0-24mA Range, Mid Scale Code
Figure 32. IOUT Noise, 0.1 Hz to 10 Hz
DAC8775 C067_IOUT_clk_feedthrough.png
0-24 mA Range, Mid Scale Code, SCLK = 1 MHz
Figure 34. Clock Feedthrough IOUT, 1MHz
DAC8775 C059_IOUT_Enable_glitch.png
0-24 mA Range
Figure 31. IOUT Enable Glitch
DAC8775 C062_IOUT_noise_PSD.png
0-24 mA Range
Figure 33. IOUT Noise Density vs Frequency
AVDD/PVDD_x = +15 V, PBKG = PVSS_x = 0 V, External DVDD = 5 V, VOUT disabled, IOUT RL = 250 Ω, TA = 25℃, REFIN = +5 V external, Buck-Boost Converter enabled (Full Tracking Mode), unless otherwise stated.
DAC8775 C033_DCDC_IOUT_INL_v_code.png
Figure 35. IOUT Linearity Error vs Digital Input Code
DAC8775 C034_DCDC_IOUT_TUE_v_code.png
Figure 37. IOUT Total Unadjusted Error vs Digital Input Code
DAC8775 C032_DCDC_IOUT_DNL_v_code.png
Figure 36. IOUT Differential Linearity Error vs Digital Input Code
AVDD/PVDD_x = +15 V, PBKG = PVSS_x = 0 V, External DVDD = 5 V, VOUT disabled, IOUT RL = 250 Ω, TA = 25℃, REFIN = +5 V external, Buck-Boost Converter enabled (Full Tracking Mode), unless otherwise stated.
DAC8775 C053_DCDC_24mA_rising_settling.png
0-24 mA Range
Figure 38. IOUT Full-Scale Settling Time, Rising Edge
DAC8775 C054_DCDC_24mA_falling_settling.png
0-24 mA Range
Figure 40. IOUT Full-Scale Settling Time, Falling Edge
DAC8775 C063_IOUT_DCDC_noise_PSD.png
0-24 mA Range
Figure 42. IOUT Noise Density vs Frequency
DAC8775 C056_DCDCBP24mA_rising_settling.png
IOUT RL = 625 Ω
Figure 39. IOUT Full-Scale Settling Time, Rising Edge
DAC8775 C055_DCDBP24mA_falling_settling.png
IOUT RL = 625 Ω
Figure 41. IOUT Full-Scale Settling Time, Falling Edge
DAC8775 C061_IOUT_Ripple.png
0-24 mA Range, Mid Scale Code
Figure 43. IOUT Ripple
AVDD/PVDD_x/VPOS_IN_x = +15 V, VNEG_IN_x = –15 V, VSENSEN_x = PBKG = PVSS_x = 0 V, External DVDD = 5 V. VOUT No load, IOUT disabled; TA = 25℃, REFIN = +5 V external;, Buck-Boost Converter disabled unless otherwise stated.
DAC8775 C005_VOUT_INL_v_code.png
Figure 44. VOUT Linearity Error vs Digital Input Code
DAC8775 C004_VOUT_TUE_v_code.png
Figure 46. VOUT Total Unadjusted Error vs Digital Input Code
DAC8775 C008_VOUT_DNL_v_temp.png
Figure 48. VOUT Differential Linearity Error vs Temperature
DAC8775 C006_VOUT_DNL_v_code.png
Figure 45. VOUT Differential Linearity Error vs Digital Input Code
DAC8775 C011_VOUT_INL_v_temp.png
Figure 47. VOUT Linearity Error vs Temperature
DAC8775 C013_VOUT_TUE_v_temp.png
Figure 49. VOUT Total Unadjusted Error vs Temperature
AVDD/PVDD_x/VPOS_IN_x = +15 V, VNEG_IN_x = –15 V, VSENSEN_x = PBKG = PVSS_x = 0 V, External DVDD = 5 V. VOUT No load, IOUT disabled; TA = 25℃, REFIN = +5 V external; Buck-Boost Converter disabled unless otherwise stated.
DAC8775 C010_VOUT_GE_v_temp.png
Figure 50. VOUT Gain Error vs Temperature
DAC8775 C009_VOUT_FSE_v_temp.png
Figure 52. VOUT Full Scale Error vs Temperature
DAC8775 C012_VOUT_MFSE_v_temp.png
Figure 54. VOUT Negative Full Scale Error vs Temperature
DAC8775 C014_VOUT_ZCE_v_temp.png
Figure 51. VOUT Zero Code Error vs Temperature
DAC8775 C007_VOUT_BPZ_v_temp.png
Figure 53. VOUT Bipolar Zero Error vs Temperature
DAC8775 C018_Short_circuit_VOUT.png
±10-V Range, Full Scale Code for VOUT sourcing & Zero Scale Code for VOUT Sinking
Figure 55. VOUT Output Voltage vs Load Current
AVDD/PVDD_x/VPOS_IN_x = +15 V, VNEG_IN_x = –15 V, VSENSEN_x = PBKG = PVSS_x = 0 V, External DVDD = 5 V. VOUT No load, IOUT disabled; TA = 25℃, REFIN = +5 V external; Buck-Boost Converter disabled unless otherwise stated.
DAC8775 C016_VOUT_INL_v_PS.png
|VPOS_IN_x| = VNEG_IN_x
Figure 56. VOUT Linearity Error vs Power Supplies
DAC8775 C017_VOUT_TUE_v_PS.png
|VPOS_IN_x| = VNEG_IN_x
Figure 58. VOUT Total Unadjusted Error vs Power Supplies
DAC8775 C029_VPOS_IDD_v_temp.png
|VPOS_IN_x| = VNEG_IN_x, 10-V Range, Mid Scale Code
Figure 60. VOUT Power Supply Current vs Temperature
DAC8775 C015_VOUT_DNL_v_PS.png
|VPOS_IN_x| = VNEG_IN_x
Figure 57. VOUT Differential Linearity Error vs Power Supplies
DAC8775 C028_VPOS_IDD_v_code.png
|VPOS_IN_x| = VNEG_IN_x, 10-V Range
Figure 59. VOUT Power Supply Current vs Digital Input Code
DAC8775 C030_VPOS_IDD_v_VPOS_VNEG.png
|VPOS_IN_x| = VNEG_IN_x, 10-V Range, Mid Scale Code
Figure 61. VOUT Power Supply Current vs Power Supplies Voltages
AVDD/PVDD_x/VPOS_IN_x = +15 V, VNEG_IN_x = –15 V, VSENSEN_x = PBKG = PVSS_x = 0 V, External DVDD = 5 V. VOUT No load, IOUT disabled; TA = 25℃, REFIN = +5 V external;, Buck-Boost Converter disabled unless otherwise stated.
DAC8775 C018_VOUT_rising_settling.png
10-V Range, Load 1K//200pF
Figure 62. VOUT Full-Scale Settling Time, Rising Edge
DAC8775 C020_VOUT_7FFF_8000.png
10-V Range, 7FFFh - 8000h
Figure 64. VOUT Glitch Impulse, Rising Edge, 1LSB Step
DAC8775 C022_VOUT_Power_ON_Glitch.png
Figure 66. VOUT Power-On Glitch
DAC8775 C019_VOUT_falling_settling.png
10-V Range, Load 1K//200pF
Figure 63. VOUT Full-Scale Settling Time, Falling Edge
DAC8775 C021_VOUT_8000_7FFF.png
10-V Range, 8000h - 7FFFh
Figure 65. VOUT Glitch Impulse, Falling Edge, 1LSB Step
DAC8775 C023_VOUT_Enable_glitch.png
10V Range
Figure 67. VOUT Enable Glitch
AVDD/PVDD_x/VPOS_IN_x = +15 V, VNEG_IN_x = –15 V, VSENSEN_x = PBKG = PVSS_x = 0 V, External DVDD = 5 V. VOUT No load, IOUT disabled; TA = 25℃, REFIN = +5 V external; Buck-Boost Converter disabled unless otherwise stated.
DAC8775 C024_VOUT_pk_noise.png
10-V Range, Mid Scale Code
Figure 68. VOUT Noise, 0.1 Hz to 10 Hz
DAC8775 C031_VOUT_clk_feedthrough.png
10-V Range, Mid Scale Code, SCLK = 1MHz
Figure 70. Clock Feedthrough VOUT, 1MHz
DAC8775 C026_VOUT_noise_PSD.png
10-V Range
Figure 69. VOUT Noise Density vs Frequency
AVDD/PVDD_x = +15 V, VSENSEN_x = PBKG = PVSS_x = 0 V, External DVDD = 5 V. VOUT No load, IOUT disabled; TA = 25℃, REFIN = +5 V external; Buck-Boost Converter enabled (Full Tracking Mode), unless otherwise stated.
DAC8775 C002_DCDC_VOUT_INL_v_code.png
Figure 71. VOUT Linearity Error vs Digital Input Code
DAC8775 C003_DCDC_VOUT_TUE_v_code.png
Figure 73. VOUT Total Unadjusted Error vs Digital Input Code
DAC8775 C025_VOUT_Ripple.png
10-V Range, Mid Scale Code
Figure 75. VOUT Ripple
DAC8775 C001_DCDC_VOUT_DNL_v_code.png
Figure 72. VOUT Differential Linearity Error vs Digital Input Code
DAC8775 C027_VOUT_DCDC_noise_PSD.png
10-V Range
Figure 74. VOUT Noise Density vs Frequency
AVDD/PVDD_x/VPOS_IN_x = +15 V, VNEG_IN_x = –15 V, PBKG = PVSS_x = 0 V, External DVDD = 5 V. VOUT disabled, IOUT disabled, TA = 25℃, Buck-Boost Converter disabled, unless otherwise stated.
DAC8775 C068_VREF_drift.png
30 Units
Figure 76. Internal Reference Voltage vs Temperature
DAC8775 C070_VREF_line_regulation.png
Figure 78. Internal Reference Voltage vs Power Supply
DAC8775 C073_VREF_pk_noise.png Figure 80. Internal Reference Noise, 0.1 Hz to 10 Hz
DAC8775 C069_VREF_load_regulation.png
Figure 77. Internal Reference Voltage vs Load Current
DAC8775 C072_VREF_DCDC_noise_PSD.png
Figure 79. Internal Reference Noise Density vs Frequency
AVDD/PVDD_x = +15 V, PBKG = PVSS_x = 0 V, External DVDD = 5 V, VOUT disabled, IOUT RL = 250Ω, TA = 25℃, Buck-Boost Converter enabled (Full Tracking Mode), unless otherwise stated.
DAC8775 C071_VREF_noise_PSD.png
0-24 mA Range, Full Scale Code on all channels
Figure 81. Internal Reference Noise Density vs Frequency
DAC8775 C074_VREF_Ripple.png
0-24 mA Range, Full Scale Code on all channels
Figure 82. Internal Reference Ripple
AVDD/PVDD_x = +15 V, PBKG = PVSS_x = 0 V, External DVDD = 5 V, TA = 25℃, Buck-Boost Converter enabled (Full Tracking Mode), unless otherwise stated.
DAC8775 C075_VPOS_VNEG_powerup_enable.png
Figure 83. Buck-Boost Converter Power-On (IOUT Mode)
DAC8775 C106_VPOS_IOUT_noise_PSD_250.png
0-24 mA Range, RL = 250 Ω
Figure 85. VPOS Noise Density (IOUT Mode) vs Frequency
DAC8775 C116_VNEG_VOUT_noise_PSD.png
10-V Range, No Load
Figure 87. VNEG Noise Density (VOUT Mode) vs Frequency
DAC8775 C108_VOUT_Enable_w_DCDC.png
Figure 84. Buck-Boost Converter Power-On (VOUT Mode)
DAC8775 C115_VPOS_VOUT_noise_PSD.png
10-V Range, No Load
Figure 86. VPOS Noise Density (VOUT Mode) vs Frequency
AVDD/PVDD_x = +15 V, VNEG_IN_x = PBKG = PVSS_x = 0 V, External DVDD = 5 V, VOUT disabled, IOUT enabled 0-24 mA Range, TA = 25℃, REFIN = +5 V external, Buck-Boost Converter VPOS_IN_x enabled (Full Tracking Mode), unless otherwise stated.
DAC8775 C076_IOUT_Efficiency_250ohm.png
Figure 88. IOUT Efficiency vs Load Current
DAC8775 C083_IOUT_Efficiency_temp_250.png
Full Scale Code IOUT = 24 mA
Figure 90. IOUT Efficiency vs Temperature
DAC8775 C090_VPOS_pwrLoss_1ohm.png
Full Scale Code IOUT = 24 mA
Figure 92. PVDD Power Loss (IOUT Mode) vs Load Current
DAC8775 C079_VPOS_Efficiency_1ohm.png
Figure 89. VPOS Efficiency (IOUT Mode) vs Load Current
DAC8775 C087_VPOS_Efficiency_temp_250.png
Full Scale Code IOUT = 24 mA
Figure 91. VPOS Efficiency (IOUT Mode) vs Temperature
DAC8775 C102_VPOS_pwrLoss_v_temp_1ohm.png
Full Scale Code, 24 mA on all channels
Figure 93. PVDD Power Loss (IOUT Mode) vs Temperature
AVDD/PVDD_x = +15 V, PBKG = PVSS_x = 0 V, External DVDD = 5 V, VOUT enabled, 10-V Range, Load 1K//200pF, IOUT disabled, TA = 25℃, REFIN = +5 V external, Buck-Boost Converter enabled (Full Tracking Mode), unless otherwise stated.
DAC8775 C094_IOUT_dieTemp_250ohm.png
VOUT disabled, IOUT = 24 mA (all channels), VNEG_IN_x = 0 V
Figure 94. Intenal Die Temperature (IOUT Mode) vs Load Current
DAC8775 C111_VOUT_VPOS_loss_load_1k.png
Full Scale Code on all channels
Figure 96. PVDD Power Loss (VOUT Mode) vs Load Current
DAC8775 C112_VOUT_VPOS_dieT_load_1k.png
All channels enabled
Figure 98. Internal Die Temperature (VOUT Mode) vs Load Current
DAC8775 C109_VOUT_VPOS_Eff_load_1k.png
Figure 95. VPOS Efficiency (VOUT Mode) vs Load Current
DAC8775 C114_VOUT_VPOS_Loss_temp.png
Full Scale Code on all channels
Figure 97. PVDD Power Loss (VOUT Mode) vs Temperature
DAC8775 C120_5p5_IDVDD_v_LogicLevel.png
Figure 99. Power Supply Current (DVDD) vs Input Logic Level