SLAS693C March   2010  – March  2015 DAC3283

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics - DC Specifications
    6. 7.6 Electrical Characteristics - AC Specifications
    7. 7.7 Electrical Characteristics - Digital Specifications
    8. 7.8 Timing Requirements
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Definition Of Specifications
        1. 8.3.1.1  Adjacent Carrier Leakage Ratio (ACLR)
        2. 8.3.1.2  Analog and Digital Power Supply Rejection Ratio (APSSR, DPSSR)
        3. 8.3.1.3  Differential Nonlinearity (DNL)
        4. 8.3.1.4  Gain Drift
        5. 8.3.1.5  Gain Error
        6. 8.3.1.6  Integral Nonlinearity (INL)
        7. 8.3.1.7  Intermodulation Distortion (IMD3, IMD)
        8. 8.3.1.8  Offset Drift
        9. 8.3.1.9  Offset Error
        10. 8.3.1.10 Output Compliance Range
        11. 8.3.1.11 Reference Voltage Drift
        12. 8.3.1.12 Spurious Free Dynamic Range (SFDR)
        13. 8.3.1.13 Noise Spectral Density (NSD)
    4. 8.4 Device Functional Modes
      1. 8.4.1  Serial Interface
      2. 8.4.2  Data Interface
      3. 8.4.3  Input FIFO
      4. 8.4.4  FIFO Alarms
      5. 8.4.5  FIFO Modes of Operation
        1. 8.4.5.1 Dual Sync Souces Mode
        2. 8.4.5.2 Single Sync Source Mode
        3. 8.4.5.3 Bypass Mode
      6. 8.4.6  Multi-Device Operation
        1. 8.4.6.1 Multi-Device Synchronization: Dual Sync Sources Mode
        2. 8.4.6.2 Multi-Device Operation: Single Sync Source Mode
      7. 8.4.7  Data Pattern Checker
      8. 8.4.8  DATACLK Monitor
      9. 8.4.9  FIR Filters
      10. 8.4.10 Coarse Mixer
      11. 8.4.11 Quadrature Modulation Correction (QMC)
      12. 8.4.12 Digital Offset Control
      13. 8.4.13 Temperature Sensor
      14. 8.4.14 Sleep Modes
      15. 8.4.15 LVPECL Inputs
      16. 8.4.16 LVDS INPUTS
      17. 8.4.17 CMOS Digital Inputs
      18. 8.4.18 Reference Operation
      19. 8.4.19 DAC Transfer Function
      20. 8.4.20 Analog Current Outputs
      21. 8.4.21 Passive Interface to Analog Quadrature Modulators
    5. 8.5 Register Maps
      1. 8.5.1  CONFIG0 (address = 0x00) [reset = 0x70]
      2. 8.5.2  CONFIG1 (address = 0x01) [reset = 0x11]
      3. 8.5.3  CONFIG2 (address = 0x02) [reset = 0x00]
      4. 8.5.4  CONFIG3 (address = 0x03) [reset = 0x10]
      5. 8.5.5  CONFIG4 (address = 0x04) [reset = 0xFF]
      6. 8.5.6  CONFIG5 (address = 0x05) READ ONLY
      7. 8.5.7  CONFIG6 (address =0x06) [reset = 0x00]
      8. 8.5.8  CONFIG7 (address = 0x07) [reset = 0x00] (WRITE TO CLEAR)
      9. 8.5.9  CONFIG8 (address = 0x08) [reset = 0x00] (WRITE TO CLEAR)
      10. 8.5.10 CONFIG9 (address = 0x09) [reset = 0x7A]
      11. 8.5.11 CONFIG10 (address = 0x0A) [reset = 0xB6]
      12. 8.5.12 CONFIG11 (address = 0x0B) [reset = 0xEA]
      13. 8.5.13 CONFIG12 (address =0x0C) [reset = 0x45]
      14. 8.5.14 CONFIG13 (address =0x0D) [reset = 0x1A]
      15. 8.5.15 CONFIG14 Register Name (address = 0x0E) [reset = 0x16]
      16. 8.5.16 CONFIG15 Register Name (address = 0x0F) [reset = 0xAA]
      17. 8.5.17 CONFIG16 (address = 0x10) [reset = 0xV6]
      18. 8.5.18 CONFIG17 (address = 0x11) [reset = 0x24]
      19. 8.5.19 CONFIG18 (address = 0x12) [reset = 0x02]
      20. 8.5.20 CONFIG19 (address = 0x13) [reset = 0x00]
      21. 8.5.21 CONFIG20 (address = 0x14) [reset = 0x00] (CAUSES AUTOSYNC)
      22. 8.5.22 CONFIG21 (address = 0x15) [reset = 0x00]
      23. 8.5.23 CONFIG22 (address = 0x16) [reset = 0x00]
      24. 8.5.24 CONFIG23 (address = 0x17) [reset = 0x00]
      25. 8.5.25 CONFIG24 (address = 0x18) [reset = 0x83]
      26. 8.5.26 CONFIG25 (address = 0x19) [reset = 0x00]
      27. 8.5.27 CONFIG26 (address = 0x1a) [reset = 0x00]
      28. 8.5.28 CONFIG27 (address =0x1b) [reset = 0x00] (CAUSES AUTOSYNC)
      29. 8.5.29 CONFIG28 (address = 0x1C) [reset = 0x00]
      30. 8.5.30 CONFIG29 (address = 0x1D) [reset = 0x00]
      31. 8.5.31 CONFIG30 (address = 0x1E) [reset = 0x24]
      32. 8.5.32 VERSION31 (address = 0x1F) [reset = 0x12] (PARTIAL READ ONLY)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Direct Conversion Radio
      3. 9.2.3 Application Performance Plots
  10. 10Power Supply Recommendations
    1. 10.1 Power-up Sequence
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Supply voltage range DACDVDD18(2) –0.5 2.3 V
DIGVDD18(2) –0.5 2.3 V
CLKVDD18(2) –0.5 2.3 V
VFUSE(2) –0.5 2.3 V
AVDD33(2) –0.5 4 V
Terminal voltage range CLKVDD18 to DIGDVDD18 –0.5 0.5 V
DACVDD18 TO DIGVDD18 –0.5 0.5 V
D[7..0]P ,D[7..0]N, DATACLKP, DATACLKN, FRAMEP, FRAMEN(2) –0.5 DIGVDD18 + 0.5 V
DACCLKP, DACCLKN, OSTRP, OSTRN(2) –0.5 CLKVDD18 + 0.5 V
ALARM_SDO, SDIO, SCLK, SDENB, TXENABLE(2) –0.5 DIGCLKVDD18 + 0.5 V
IOUTA1/B1, IOUTA2/B2(2) –1.0 AVDD33 + 0.5 V
EXTIO, BIASJ(2) –0.5 AVDD33 + 0.5 V
Peak input current (any input) 20 mA
Peak total input current (all inputs) –30 mA
Operating free-air temperature range, TA: DAC3283 –40 85 °C
Storage temperature range, TSTG –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Measured with respect to GND.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Voltage 1.8-V DAC core supply voltage, DACDVDD18 1.7 1.8 1.9 V
1.8-V digital supply voltage, DIGVDD18 1.7 1.8 1.9 V
1.8-V internal clock buffer supply voltage, CLKVDD18 1.7 1.8 1.9 V
3.3-V analog supply voltage, AVDD33 3.0 3.3 3.6 V

7.4 Thermal Information

THERMAL METRIC(1) RGZ (VQFN) UNIT
48 PINS
RθJA Junction-to-ambient thermal resistance 26.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 12.2
RθJB Junction-to-board thermal resistance 3.7
ψJT Junction-to-top characterization parameter 0.2
ψJB Junction-to-board characterization parameter 3.6
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.7
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics – DC Specifications

over operating free-air temperature range, nominal supplies, IOUTFS = 20 mA (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RESOLUTION 16 Bits
DC ACCURACY
DNL Differential nonlinearity 1 LSB = IOUTFS/216 ±2 LSB
INL Integral nonlinearity ±4
ANALOG OUTPUT
Coarse gain linearity ±0.04 LSB
Offset error Mid code offset ±0.01 %FSR
Gain error With external reference ±2 %FSR
With internal reference ±2 %FSR
Gain mismatch With internal reference –2 2 %FSR
Minimum full scale output current Nominal full-scale current, IOUTFS = 16 x IBIAS current. 2 mA
Maximum full scale output current 20 mA
Output compliance range(1) IOUTFS = 20 mA AVDD –0.5V AVDD +0.5V V
Output resistance 300 kΩ
Output capacitance 5 pF
REFERENCE OUTPUT
Vref Reference output voltage 1.14 1.2 1.26 V
Reference output current(2) 100 nA
REFERENCE INPUT
VEXTIO Input voltage range External reference mode 0.1 1.2 1.25 V
Input resistance 1 MΩ
Small signal bandwidth 472 kHz
Input capacitance 100 pF
TEMPERATURE COEFFICIENTS
Offset drift With external reference ±1 ppm of
FSR/°C
Gain drift With internal reference ±15 ppm of
FSR/°C
±30
Reference voltage drift ±8 ppm/°C
POWER SUPPLY
AVDD33 3.0 3.3 3.6 V
DACVDD18, DIGVDD18, CLKVDD18 1.7 1.8 1.9 V
I(AVDD33) Analog supply current Mode 1 (below) 149 mA
I(DIGDVDD) Digital supply current 340 mA
I(DACVDD18) DAC supply current 55 mA
I(CLKVDD18) Clock supply current 37 mA
P Power dissipation Mode 1: fDAC = 800MSPS,
4x interpolation, Fs/4 mixer on, QMC on 		1300 1450 mW
Mode 2: fDAC = 491.52MSPS,
2x interpolation, Mixer off, QMC on		 1000 mW
Mode 3: Sleep mode
fDAC = 800MSPS, 4x interpolation, Fs/4 mixer on,
CONFIG24 sleepa, sleepb set = 1		 750 mW
Mode 4: Power-Down mode
No clock, static data pattern,
CONFIG23 clkpath_sleep_a, clkpath_sleepb set = 1
CONFIG24 clkrecv_sleep, sleepa, sleepb set = 1 		7 18 mW
PSRR Power supply rejection ratio DC tested ±0.2 %FSR/V
T Operating range –40 25 85 °C
(1) The lower limit of the output compliance is determined by the CMOS process. Exceeding this limit may result in transistor breakdown, resulting in reduced reliability of the DAC3283 device. The upper limit of the output compliance is determined by the load resistors and full-scale output current. Exceeding the upper limit adversely affects distortion performance and integral nonlinearity.
(2) Use an external buffer amplifier with high impedance input to drive any external load.

7.6 Electrical Characteristics – AC Specifications

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG OUTPUT(1)
fDAC Maximum DAC output update rate 1x Interpolation 312.5 MSPS
2x Interpolation 625
4x Interpolation 800
ts(DAC) Output settling time to 0.1% Transition: Code 0x0000 to 0xFFFF 10.4 ns
tpd Output propagation delay DAC outputs are updated on the falling edge of DAC clock. Does not include digital latency (see below). 2 ns
tr(IOUT) Output rise time 10% to 90% 220 ps
tf(IOUT) Output fall time 90% to 10% 220 ps
Power-up time DAC wake-up time IOUT current settling to 1% of IOUTFS. Measured from SDENB rising edge; Register CONFIG24, toggle sleepa from 1 to 0. 90 µs
DAC sleep time IOUT current settling to less than 1% of IOUTFS. Measured from SDENB rising edge; Register CONFIG24, toggle sleepa from 0 to 1. 90
Digital latency 1x Interpolation 59 DAC clock cycles
2x Interpolation 139
4x Interpolation 290
QMC 24
AC PERFORMANCE(2)
SFDR Spurious free dynamic range (0 to fDAC/2)Tone at 0 dBFS fDAC = 800 MSPS, fOUT = 20.1 MHz 85 dBc
fDAC = 800 MSPS, fOUT = 50.1 MHz 76
fDAC = 800 MSPS, fOUT = 70.1 MHz 72
IMD3 Third-order two-tone intermodulation distortion
Each tone at –12 dBFS		 fDAC = 800 MSPS, fOUT = 30 ± 0.5 MHz 93 dBc
fDAC = 800 MSPS, fOUT = 50 ± 0.5 MHz 90
fDAC = 800 MSPS, fOUT = 100 ± 0.5 MHz 86
NSD Noise spectral density tone at 0dBFS fDAC = 800 MSPS, fOUT = 10.1 MHz 162 dBc/Hz
fDAC = 800 MSPS, fOUT = 80.1 MHz 160
WCDMA(3) Adjacent channel leakage ratio, single carrier fDAC = 737.28 MSPS, fOUT = 30.72MHz 85 dBc
fDAC = 737.28 MSPS, fOUT = 153.6MHz 81
Alternate channel leakage ratio, single carrier fDAC = 737.28 MSPS, fOUT = 30.72MHz 91 dBc
fDAC = 737.28 MSPS, fOUT = 153.6MHz 85
Channel isolation fDAC = 800 MSPS, fOUT = 10MHz 84 dBc
(1) Measured single-ended into 50Ω load.
(2) 4:1 transformer output termination, 50Ω doubly terminated load
(3) Single carrier, W-CDMA with 3.84 MHz BW, 5-MHz spacing, centered at fOUT, PAR = 12dB. TESTMODEL 1, 10 ms

7.7 Electrical Characteristics – Digital Specifications

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LVDS INTERFACE:D[7:0]P/N, DATACLKP/N, FRAMEP/N (1)
fDATA Input data rate Byte-wide DDR format
DATACLK frequency = 625 MHz		 312.5 MSPS
fBUS Byte-wide LVDS data transfer rate 1250 MSPS
VA,B+ Logic high differential input voltage threshold 150 400 mV
VA,B– Logic low differential input voltage threshold –150 –400 mV
VCOM Input common mode 0.9 1.2 1.5 V
ZT Internal termination 85 110 135 Ω
CL LVDS Input capacitance 2 pF
TIMING LVDS INPUTS: DATACLKP/N DOUBLE EDGE LATCHING – See Figure 40
ts(DATA) Setup time, D[7:0]P/N and FRAMEP/N, valid to either edge of DATACLKP/N FRAMEP/N latched on rising edge of DATACLKP/N only –25 ps
th(DATA) Hold time, D[7:0]P/N and FRAMEP/N, valid after either edge of DATACLKP/N FRAMEP/N latched on rising edge of DATACLKP/N only 375 ps
t(FRAME) FRAMEP/N pulse width fDATACLK is DATACLK frequency in MHz 1/2fDATACLK ns
t_align Maximum offset between DATACLKP/N and DACCLKP/N rising edges FIFO bypass mode only fDACCLK is DACCLK frequency in MHz 1/2fDACCLK –0.55 ns
CLOCK INPUT (DACCLKP/N)
Duty cycle 40% 60%
Differential voltage(2) 0.4 1.0 V
DACCLKP/N Input Frequency 800 MHz
OUTPUT STROBE (OSTRP/N)
fOSTR Frequency fOSTR = fDACCLK / (n × 8 × Interp) where n is any positive integer fDACCLK is DACCLK frequency in MHz fDACCLK / (8 x interp)
Duty cycle 40% 60%
Differential voltage 0.4 1.0 V
TIMING OSTRP/N INPUT: DACCLKP/N RISING EDGE LATCHING
ts(OSTR) Setup time, OSTRP/N valid to rising edge of DACCLKP/N 200 ps
th(OSTR) Hold time, OSTRP/N valid after rising edge of DACCLKP/N 200 ps
CMOS INTERFACE: ALARM_SDO, SDIO, SCLK, SDENB, TXENABLE
VIH High-level input voltage 1.25 V
VIL Low-level input voltage 0.54 V
IIH High-level input current –40 40 μA
IIL Low-level input current –40 40 μA
CI CMOS input capacitance 2 pF
VOH ALARM_SDO, SDIO Iload = –100 μA DIGVDD18
–0.2		 V
Iload = –2mA 0.8 x
DIGVDD18		 V
VOL ALARM_SDO, SDIO Iload = 100 μA 0.2 V
Iload = 2 mA 0.5 V
(1) See LVDS INPUTS section for terminology.
(2) Driving the clock input with a differential voltage lower than 1V will result in degraded performance.

7.8 Timing Requirements

MIN NOM MAX UNIT
SERIAL PORT TIMING – See Figure 26 and Figure 27
ts(SDENB) Setup time, SDENB to rising edge of SCLK 20 ns
ts(SDIO) Setup time, SDIO valid to rising edge of SCLK 10 ns
th(SDIO) Hold time, SDIO valid to rising edge of SCLK 5 ns
t(SCLK) Period of SCLK Register CONFIG5 read (temperature sensor read) 1 µs
All other registers 100 ns
t(SCLKH) High time of SCLK Register CONFIG5 read (temperature sensor read) 0.4 µs
All other registers 40 ns
t(SCLKL) Low time of SCLK Register CONFIG5 read (temperature sensor read) 0.4 µs
All other registers 40 ns
td(Data) Data output delay after falling edge of SCLK 10 ns

7.9 Typical Characteristics

DAC3283 INL_las693.gif
Figure 1. Integral Non-Linearity
DAC3283 FSDR_f_las693.gif
Figure 3. Spurious Free Dynamic Range vs Input Scale
DAC3283 har3_fo_las693.gif
Figure 5. Third Harmonic vs Input Scale
DAC3283 FSDR3_f_las693.gif
Figure 7. Spurious Free Dynamic Range vs fDAC
DAC3283 pwr_f_las693.gif
Figure 9. Single Tone Spectral Plot
DAC3283 pwr3_f_las693.gif
Figure 11. Single Tone Spectral Plot
DAC3283 IMD3B_fo_las693.gif
Figure 13. IMD3 vs Interpolation
DAC3283 IMD3D_fo_las693.gif
Figure 15. IMD3 vs IOUTFS
DAC3283 NSD2_fo_las693.gif
Figure 17. NSD vs Interpolation
DAC3283 ACLR_fo_las693.gif
Figure 19. Single Carrier WCDMA ACLR vs Input Scale
DAC3283 fdac_po_las693.gif
Figure 21. Power vs fDAC
DAC3283 fdac3_po_las693.gif
Figure 23. DACVDD18 vs fDAC
DAC3283 fdac5_po_las693.gif
Figure 25. AVDD33 vs fDAC
DAC3283 DNL_las693.gif
Figure 2. Differential Non-Linearity
DAC3283 dis_fo_las693.gif
Figure 4. Second Harmonic vs Input Scale
DAC3283 FSDR2_f_las693.gif
Figure 6. Spurious Free Dynamic Range vs Interpolation
DAC3283 FSDR4_f_las693.gif
Figure 8. Spurious Free Dynamic Range vs IOUTFS
DAC3283 pwr2_f_las693.gif
Figure 10. Single Tone Spectral Plot
DAC3283 IMD3_fo_las693.gif
Figure 12. IMD3 vs Input Scale
DAC3283 IMD3C_fo_las693.gif
Figure 14. IMD3 vs fDAC
DAC3283 NSD_fo_las693.gif
Figure 16. NSD vs Input Scale
DAC3283 NSD3_fo_las693.gif
Figure 18. NSD vs fDAC
DAC3283 ACLR2_fo_las693.gif
Figure 20. Four Carrier WCDMA ACLR vs Input Scale
DAC3283 fdac2_po_las693.gif
Figure 22. DVDD18 vs fDAC
DAC3283 fdac4_po_las693.gif
Figure 24. CLKVDD18 vs fDAC