SNAS265J June 2005 – September 2015 DAC121S101 , DAC121S101-Q1
PRODUCTION DATA.
| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| Supply Voltage, VA | 6.5 | V | ||
| Voltage on any Input Pin | −0.3 | (VA + 0.3) | V | |
| Input Current at Any Pin (3) | 10 | mA | ||
| Package Input Current (3) | 20 | mA | ||
| Power Consumption at TA = 25°C | See (4) | |||
| Soldering Temperature, Infrared, 10 Seconds(5) | 235 | °C | ||
| Storage Temperature, Tstg | −65 | 150 | °C | |
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2500 | V |
| Machine Model | ±250 | |||
| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| Operating Temperature Range | DAC121S101 | −40 | TA | 105 | °C |
| DAC121S101-Q1 | −40 | TA | 125 | °C | |
| Supply Voltage, VA | 2.7 | 5.5 | V | ||
| Any Input Voltage(6) | −0.1 | (VA + 0.1) | V | ||
| Output Load | 0 | 1500 | pF | ||
| SCLK Frequency | 30 | MHz | |||
| THERMAL METRIC(1) | DAC121S101, DAC121S101-Q1 | UNIT | ||
|---|---|---|---|---|
| DGK (VSSOP) | DDC (SOT) | |||
| 8 PINS | 6 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 240 | 250 | °C/W |
| PARAMETER | TEST CONDITIONS | MIN(7) | TYP(7) | MAX(7) | UNIT | |||
|---|---|---|---|---|---|---|---|---|
| STATIC PERFORMANCE | ||||||||
| Resolution | TMIN ≤ TA ≤ TMAX | 12 | Bits | |||||
| Monotonicity | TMIN ≤ TA ≤ TMAX | 12 | Bits | |||||
| INL | Integral Non-Linearity | Over Decimal codes 48 to 4047 | TA = 25°C | ±2.6 | LSB | |||
| TMIN ≤ TA ≤ TMAX | ±8 | |||||||
| DNL | Differential Non-Linearity | VA = 2.7 V to 5.5 V | TA = 25°C | −0.15 | +0.25 | LSB | ||
| TMIN ≤ TA ≤ TMAX | −0.7 | +1 | LSB | |||||
| VA = 4.5 V to 5.5 V (8) | TA = 25°C | ±0.11 | LSB | |||||
| TMIN ≤ TA ≤ TMAX | ±0.5 | |||||||
| ZE | Zero Code Error | IOUT = 0 | TA = 25°C | +4 | mV | |||
| TMIN ≤ TA ≤ TMAX | +15 | |||||||
| FSE | Full-Scale Error | IOUT = 0 | TA = 25°C | −0.06 | %FSR | |||
| TMIN ≤ TA ≤ TMAX | −1 | |||||||
| GE | Gain Error | All ones Loaded to DAC register | TA = 25°C | −0.1 | %FSR | |||
| TMIN ≤ TA ≤ TMAX | ±1 | |||||||
| ZCED | Zero Code Error Drift | −20 | µV/°C | |||||
| TC GE | Gain Error Tempco | VA = 3 V | −0.7 | ppm/°C | ||||
| VA = 5 V | −1 | ppm/°C | ||||||
| OUTPUT CHARACTERISTICS | ||||||||
| Output Voltage Range(8) | TMIN ≤ TA ≤ TMAX | 0 | VA | V | ||||
| ZCO | Zero Code Output | VA = 3 V, IOUT = 10 µA | 1.8 | mV | ||||
| VA = 3 V, IOUT = 100 µA | 5 | mV | ||||||
| VA = 5 V, IOUT = 10 µA | 3.7 | mV | ||||||
| VA = 5 V, IOUT = 100 µA | 5.4 | mV | ||||||
| FSO | Full Scale Output | VA = 3 V, IOUT = 10 µA | 2.997 | V | ||||
| VA = 3 V, IOUT = 100 µA | 2.99 | V | ||||||
| VA = 5 V, IOUT = 10 µA | 4.995 | V | ||||||
| VA = 5 V, IOUT = 100 µA | 4.992 | V | ||||||
| Maximum Load Capacitance | RL = ∞ | 1500 | pF | |||||
| RL = 2 kΩ | 1500 | pF | ||||||
| DC Output Impedance | 1.3 | Ohm | ||||||
| IOS | Output Short Circuit Current | VA = 5 V, VOUT = 0 V, Input code = FFFh |
−63 | mA | ||||
| VA = 3 V, VOUT = 0 V, Input code = FFFh |
−50 | mA | ||||||
| VA = 5 V, VOUT = 5 V, Input code = 000h |
74 | mA | ||||||
| VA = 3 V, VOUT = 3 V, Input code = 000h |
53 | mA | ||||||
| LOGIC INPUT | ||||||||
| IIN | Input Current (8) | TMIN ≤ TA ≤ TMAX | ±1 | µA | ||||
| VIL | Input Low Voltage (8) | VA = 5 V TMIN ≤ TA ≤ TMAX |
0.8 | V | ||||
| VA = 3 V TMIN ≤ TA ≤ TMAX |
0.5 | V | ||||||
| VIH | Input High Voltage (8) | VA = 5 V TMIN ≤ TA ≤ TMAX |
2.4 | V | ||||
| VA = 3 V TMIN ≤ TA ≤ TMAX |
2.1 | V | ||||||
| CIN | Input Capacitance (8) | TMIN ≤ TA ≤ TMAX | 3 | pF | ||||
| POWER REQUIREMENTS | ||||||||
| IA | Supply Current (output unloaded) | Normal Mode fSCLK = 30 MHz |
VA = 5.5 V | TA = 25°C | 260 | µA | ||
| TMIN ≤ TA ≤ TMAX | 312 | |||||||
| VA = 3.6 V | TA = 25°C | 177 | µA | |||||
| TMIN ≤ TA ≤ TMAX | 217 | |||||||
| Normal Mode fSCLK = 20 MHz |
VA = 5.5 V | TA = 25°C | 224 | µA | ||||
| TMIN ≤ TA ≤ TMAX | 279 | |||||||
| VA = 3.6 V | TA = 25°C | 158 | µA | |||||
| TMIN ≤ TA ≤ TMAX | 197 | |||||||
| Normal Mode fSCLK = 0 |
VA = 5.5 V | 153 | µA | |||||
| VA = 3.6 V | 118 | µA | ||||||
| All PD Modes, fSCLK = 30 MHz |
VA = 5 V | 84 | µA | |||||
| VA = 3 V | 42 | µA | ||||||
| All PD Modes, fSCLK = 20 MHz |
VA = 5 V | 56 | µA | |||||
| VA = 3 V | 28 | µA | ||||||
| All PD Modes, fSCLK = 0 (8) |
VA = 5.5 V | TA = 25°C | 0.07 | µA | ||||
| TMIN ≤ TA ≤ TMAX | 1 | |||||||
| VA = 3.6 V | TA = 25°C | 0.04 | µA | |||||
| TMIN ≤ TA ≤ TMAX | 1 | |||||||
| PC | Power Consumption (output unloaded) | Normal Mode fSCLK = 30 MHz |
VA = 5.5 V | TA = 25°C | 1.43 | mW | ||
| TMIN ≤ TA ≤ TMAX | 1.72 | |||||||
| VA = 3.6 V | TA = 25°C | 0.64 | mW | |||||
| TMIN ≤ TA ≤ TMAX | 0.78 | |||||||
| Normal Mode fSCLK = 20 MHz |
VA = 5.5 V | TA = 25°C | 1.23 | mW | ||||
| TMIN ≤ TA ≤ TMAX | 1.53 | |||||||
| VA = 3.6 V | TA = 25°C | 0.57 | mW | |||||
| TMIN ≤ TA ≤ TMAX | 0.71 | |||||||
| Normal Mode fSCLK = 0 |
VA = 5.5 V | 0.84 | µW | |||||
| VA = 3.6 V | 0.42 | µW | ||||||
| All PD Modes, fSCLK = 30 MHz |
VA = 5 V | 0.42 | µW | |||||
| VA = 3 V | 0.13 | µW | ||||||
| All PD Modes, fSCLK = 20 MHz |
VA = 5 V | 0.28 | µW | |||||
| VA = 3 V | 0.08 | µW | ||||||
| All PD Modes, fSCLK = 0 (8) |
VA = 5.5 V | TA = 25°C | 0.39 | µW | ||||
| TMIN ≤ TA ≤ TMAX | 5.5 | |||||||
| VA = 3.6 V | TA = 25°C | 0.14 | µW | |||||
| TMIN ≤ TA ≤ TMAX | 3.6 | |||||||
| IOUT / IA | Power Efficiency | ILOAD = 2 mA | VA = 5 V | 91% | ||||
| VA = 3 V | 94% | |||||||
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
|---|---|---|---|---|---|---|---|---|
| fSCLK | SCLK Frequency | TMIN ≤ TA ≤ TMAX | 30 | MHz | ||||
| ts | Output Voltage Settling Time (8) | 400h to C00h code change, RL = 2 kΩ | CL ≤ 200 pF | TA = 25°C | 8 | µs | ||
| TMIN ≤ TA ≤ TMAX | 10 | |||||||
| CL = 500 pF | 12 | µs | ||||||
| 00Fh to FF0h code change, RL = 2 kΩ | CL ≤ 200 pF | 8 | µs | |||||
| CL = 500 pF | 12 | µs | ||||||
| SR | Output Slew Rate | 1 | V/µs | |||||
| Glitch Impulse | Code change from 800h to 7FFh | 12 | nV-s | |||||
| Digital Feedthrough | 0.5 | nV-s | ||||||
| tWU | Wake-Up Time | VA = 5 V | 6 | µs | ||||
| VA = 3 V | 39 | µs | ||||||
| 1/fSCLK | SCLK Cycle Time | TMIN ≤ TA ≤ TMAX | 33 | ns | ||||
| tH | SCLK High time | TA = 25°C | 5 | ns | ||||
| TMIN ≤ TA ≤ TMAX | 13 | |||||||
| tL | SCLK Low Time | TA = 25°C | 5 | ns | ||||
| TMIN ≤ TA ≤ TMAX | 13 | |||||||
| tSUCL | Set-up Time SYNC to SCLK Rising Edge | TA = 25°C | −15 | ns | ||||
| TMIN ≤ TA ≤ TMAX | 0 | |||||||
| tSUD | Data Set-up Time | TA = 25°C | 2.5 | ns | ||||
| TMIN ≤ TA ≤ TMAX | 5 | |||||||
| tDHD | Data Hold Time | TA = 25°C | 2.5 | ns | ||||
| TMIN ≤ TA ≤ TMAX | 4.5 | |||||||
| tCS | SCLK fall to rise of SYNC | VA = 5 V | TA = 25°C | 0 | ns | |||
| TMIN ≤ TA ≤ TMAX | 3 | |||||||
| VA = 3 V | TA = 25°C | –2 | ns | |||||
| TMIN ≤ TA ≤ TMAX | 1 | |||||||
| tSYNC | SYNC High Time | 2.7 ≤ VA ≤ 3.6 | TA = 25°C | 9 | ns | |||
| TMIN ≤ TA ≤ TMAX | 20 | |||||||
| 3.6 ≤ VA ≤ 5.5 | TA = 25°C | 5 | ns | |||||
| TMIN ≤ TA ≤ TMAX | 10 | |||||||
Figure 1. Input / Output Transfer Characteristic
Figure 2. DAC121S101 Timing
Figure 3. DNL at VA = 3 V
Figure 5. INL at VA = 3 V
Figure 7. TUE at VA = 3 V
Figure 9. DNL vs. VA
Figure 11. 3-V DNL vs. fSCLK
Figure 13. 3-V DNL vs. Clock Duty Cycle
Figure 15. 3-V DNL vs. Temperature
Figure 17. 5-V INL vs. fSCLK
Figure 19. 5-V INL vs. Clock Duty Cycle
Figure 21. 5-V INL vs. Temperature
Figure 23. Zero Code Error vs. Clock Duty Cycle
Figure 25. Full-Scale Error vs. fSCLK
Figure 27. Full-Scale Error vs. Temperature
Figure 29. Supply Current vs. Temperature
Figure 31. Power-On Reset
Figure 33. 5-V Wake-Up Time
Figure 4. DNL at VA = 5 V
Figure 6. INL at VA = 5 V
Figure 8. TUE at VA = 5 V
Figure 10. INL vs. VA
Figure 12. 5-V DNL vs. fSCLK
Figure 14. 5-V DNL vs. Clock Duty Cycle
Figure 16. 3-V INL vs. fSCLK
Figure 18. 3-V INL vs. Clock Duty Cycle
Figure 20. 3-V INL vs. Temperature
Figure 22. Zero Code Error vs. fSCLK
Figure 24. Zero Code Error vs. Temperature
Figure 26. Full-Scale Error vs. Clock Duty Cycle
Figure 28. Supply Current vs. VA
Figure 30. 5-V Glitch Response
Figure 32. 3-V Wake-Up Time