SNAS362 Data sheet | 德州仪器 TI.com.cn

SNAS362G May 2006 – April 2016 DAC104S085 , DAC104S085-Q1

PRODUCTION DATA.

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机械数据 (封装 | 引脚)

DGS|10
- MPDS035C
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- MPDS239E

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- QFND436

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7 Specifications

7.1 Absolute Maximum Ratings ⁽¹⁾⁽²⁾⁽³⁾

	MIN	MAX	UNIT
Supply voltage, V_A		6.5	V
Voltage on any input pin	−0.3	6.5	V
Input current at any pin⁽⁴⁾		10	mA
Package input current⁽⁴⁾		20	mA
Power consumption at T_A = 25°C	See ⁽⁵⁾
Junction temperature		150	°C
Storage temperature, T_stg	−65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are measured with respect to GND = 0 V, unless otherwise specified.

(3) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.

(4) When the input voltage at any pin exceeds 5.5 V or is less than GND, the current at that pin should be limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two.

(5) The absolute maximum junction temperature (T_Jmax) for this device is 150°C. The maximum allowable power dissipation is dictated by T_Jmax, the junction-to-ambient thermal resistance (θ_JA), and the ambient temperature (T_A), and can be calculated using the formula P_DMAX = (T_Jmax − T_A) / θ_JA. The values for maximum power dissipation is reached only when the device is operated in a severe fault condition (that is, when input or output pins are driven beyond the operating ratings, or the power supply polarity is reversed).

7.2 ESD Ratings – DAC104S085

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾⁽²⁾	±2500	V
V_(ESD)	Electrostatic discharge	Machine model (MM)	±250	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) Human body model is 100-pF capacitor discharged through a 1.5-kΩ resistor. Machine model is 220 pF discharged through 0 Ω.

7.3 ESD Ratings – DAC104S085-Q1

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per AEC Q100-002⁽¹⁾	±2500	V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.4 Recommended Operating Conditions⁽¹⁾

	MIN	MAX	UNIT
Operating temperature	–40	125	°C
Supply voltage, V_A	2.7	5.5	V
Reference voltage, V_REFIN	1	V_A	V
Digital input voltage⁽²⁾	0	5.5	V
Output load	0	1500	pF
SCLK frequency		40	MHz

(1) All voltages are measured with respect to GND = 0 V, unless otherwise specified.

(2) The inputs are protected as shown. Input voltage magnitudes up to 5.5 V, regardless of V_A, does not cause errors in the conversion result. For example, if V_A is 3 V, the digital input pins can be driven with a 5-V logic device.
DAC104S085 DAC104S085-Q1 20195304.gif

7.5 Thermal Information

THERMAL METRIC⁽¹⁾⁽²⁾⁽³⁾		DAC104S085-xx		UNIT
		DGS (VSSOP)	DSC (SON)
		10 PINS	10 PINS
R_θJA	Junction-to-ambient thermal resistance	159	48.9	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	53.3	40.7	°C/W
R_θJB	Junction-to-board thermal resistance	78.9	23.7	°C/W
ψ_JT	Junction-to-top characterization parameter	4.8	0.4	°C/W
ψ_JB	Junction-to-board characterization parameter	77.6	23.8	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	N/A	4.7	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

(2) Soldering process must comply with Reflow Temperature Profile specifications. See the Absolute Maximum Ratings for Soldering application report, SNOA549, for more information.

(3) Reflow temperature profiles are different for lead-free packages.

7.6 Electrical Characteristics

The following specifications apply for V_A = 2.7 V to 5.5 V, V_REFIN = V_A, C_L = 200 pF to GND, f_SCLK = 30 MHz, input code range from 12 to 1011. All limits are at T_A = 25°C, unless otherwise specified.

PARAMETER		TEST CONDITIONS			MIN⁽¹⁾	TYP⁽¹⁾	MAX⁽¹⁾	UNIT
STATIC PERFORMANCE
	Resolution	T_MIN ≤ T_A ≤ T_MAX			10			Bits
	Monotonicity	T_MIN ≤ T_A ≤ T_MAX			10			Bits
INL	Integral non-linearity					±0.7		LSB
INL	Integral non-linearity	T_MIN ≤ T_A ≤ T_MAX					±2	LSB
DNL	Differential non-linearity	V_A = 2.7 V to 5.5 V			−0.03	0.08		LSB
DNL	Differential non-linearity	V_A = 2.7 V to 5.5 V	T_MIN ≤ T_A ≤ T_MAX		−0.25		0.35	LSB
ZE	Zero code error	I_OUT = 0 mA				5		mV
ZE	Zero code error	I_OUT = 0 mA	T_MIN ≤ T_A ≤ T_MAX				15	mV
FSE	Full-scale error	I_OUT = 0 mA				−0.1		%FSR
FSE	Full-scale error	I_OUT = 0 mA	T_MIN ≤ T_A ≤ T_MAX				−0.75	%FSR
GE	Gain error	All ones Loaded to DAC register				−0.2		%FSR
GE	Gain error	All ones Loaded to DAC register	T_MIN ≤ T_A ≤ T_MAX				−1	%FSR
ZCED	Zero code error drift					−20		µV/°C
TC GE	Gain error tempco	V_A = 3 V				−0.7		ppm/°C
TC GE	Gain error tempco	V_A = 5 V				−1		ppm/°C
OUTPUT CHARACTERISTICS
	Output voltage range	See⁽²⁾, T_MIN ≤ T_A ≤ T_MAX			0 V_REFIN		0 V_REFIN	V
I_OZ	High-impedance output leakage current⁽²⁾	T_MIN ≤ T_A ≤ T_MAX					±1	µA
ZCO	Zero code output	V_A = 3 V, I_OUT = 200 µA				1.3		mV
		V_A = 3 V, I_OUT = 1 mA				6
		V_A = 5 V, I_OUT = 200 µA				7
		V_A = 5 V, I_OUT = 1 mA				10
FSO	Full-scale output	V_A = 3 V, I_OUT = 200 µA				2.984		V
		V_A = 3 V, I_OUT = 1 mA				2.934
		V_A = 5 V, I_OUT = 200 µA				4.989
		V_A = 5 V, I_OUT = 1 mA				4.958
I_OS	Output short-circuit current (source)	V_A = 3 V, V_OUT = 0 V, Input Code = 3FFh				–56		mA
I_OS	Output short-circuit current (source)	V_A = 5 V, V_OUT = 0 V, Input Code = 3FFh				–69		mA
I_OS	Output short-circuit current (sink)	V_A = 3 V, V_OUT = 3 V, Input Code = 000h				52		mA
I_OS	Output short-circuit current (sink)	V_A = 5 V, V_OUT = 5 V, Input Code = 000h				75		mA
I_O	Continuous output current⁽²⁾	Available on each DAC output, T_MIN ≤ T_A ≤ T_MAX					11	mA
C_L	Maximum load capacitance	R_L = ∞				1500		pF
C_L	Maximum load capacitance	R_L = 2 kΩ				1500		pF
Z_OUT	DC output impedance					7.5		Ω
REFERENCE INPUT CHARACTERISTICS
VREFIN	Input range minimum					0.2		V
	Input range minimum	T_MIN ≤ T_A ≤ T_MAX			1			V
	Input range maximum	T_MIN ≤ T_A ≤ T_MAX					V_A	V
	Input impedance					30		kΩ
LOGIC INPUT CHARACTERISTICS
I_IN	Input current⁽²⁾	T_MIN ≤ T_A ≤ T_MAX					±1	µA
V_IL	Input low voltage⁽²⁾	V_A = 3 V				0.9		V
		V_A = 3 V	T_MIN ≤ T_A ≤ T_MAX				0.6	V
		V_A = 5 V				1.5		V
		V_A = 5 V	T_MIN ≤ T_A ≤ T_MAX				0.8	V
V_IH	Input high voltage⁽²⁾	V_A = 3 V				1.4		V
		V_A = 3 V	T_MIN ≤ T_A ≤ T_MAX		2.1			V
		V_A = 5 V				2.1		V
		V_A = 5 V	T_MIN ≤ T_A ≤ T_MAX		2.4			V
C_IN	Input capacitance⁽²⁾	T_MIN ≤ T_A ≤ T_MAX					3	pF
POWER REQUIREMENTS
V_A⁽³⁾	Supply voltage minimum	T_MIN ≤ T_A ≤ T_MAX			2.7			V
V_A⁽³⁾	Supply voltage maximum	T_MIN ≤ T_A ≤ T_MAX					5.5	V
I_N	Normal supply current (output unloaded)	f_SCLK = 30 MHz	V_A = 2.7 V to 3.6 V			350		µA
			V_A = 2.7 V to 3.6 V	T_MIN ≤ T_A ≤ T_MAX			485	µA
			V_A = 4.5 V to 5.5 V			500		µA
			V_A = 4.5 V to 5.5 V	T_MIN ≤ T_A ≤ T_MAX			650	µA
		f_SCLK = 0 MHz	V_A = 2.7 V to 3.6 V			330		µA
		f_SCLK = 0 MHz	V_A = 4.5 V to 5.5 V			460		µA
I_PD	Power-down supply current (output unloaded, SYNC = DIN = 0V after PD mode loaded)	All PD Modes,⁽²⁾	V_A = 2.7 V to 3.6 V			0.1		µA
			V_A = 2.7 V to 3.6 V	T_MIN ≤ T_A ≤ T_MAX			1	µA
			V_A = 4.5 V to 5.5 V			0.15		µA
			V_A = 4.5 V to 5.5 V	T_MIN ≤ T_A ≤ T_MAX			1	µA
P_N	Normal supply power (output unloaded)	f_SCLK = 30 MHz	V_A = 2.7 V to 3.6 V			1.1		mW
			V_A = 2.7 V to 3.6 V	T_MIN ≤ T_A ≤ T_MAX			1.7	mW
			V_A = 4.5 V to 5.5 V			2.5		mW
			V_A = 4.5 V to 5.5 V	T_MIN ≤ T_A ≤ T_MAX			3.6	mW
		f_SCLK = 0 MHz	V_A = 2.7 V to 3.6 V			1		mW
		f_SCLK = 0 MHz	V_A = 4.5 V to 5.5 V			2.3		mW
P_PD	Power-down supply power (output unloaded, SYNC = DIN = 0V after PD mode loaded)	All PD Modes,⁽²⁾	V_A = 2.7 V to 3.6 V			0.3		µW
			V_A = 2.7 V to 3.6 V	T_MIN ≤ T_A ≤ T_MAX			3.6	µW
			V_A = 4.5 V to 5.5 V			0.8		µW
			V_A = 4.5 V to 5.5 V	T_MIN ≤ T_A ≤ T_MAX			5.5	µW

(1) Typical figures are at T_J = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing Quality Level).

(2) This parameter is ensured by design and/or characterization and is not tested in production.

(3) To ensure accuracy, it is required that V_A and V_REFIN be well bypassed.

7.7 Timing Requirements

Values shown in this table are design targets and are subject to change before product release.
The following specifications apply for V_A = 2.7 V to 5.5 V, V_REFIN = V_A, C_L = 200 pF to GND, f_SCLK = 30 MHz, input code range from 12 to 1011. All limits are at T_A = 25°C, unless otherwise specified.

				MIN⁽¹⁾	TYP⁽¹⁾	MAX⁽¹⁾	UNIT
f_SCLK	SCLK frequency				40		MHz
f_SCLK	SCLK frequency	T_MIN ≤ T_A ≤ T_MAX				30	MHz
t_s	Output voltage settling time⁽²⁾	100h to 300h code change R_L = 2 kΩ, C_L = 200 pF			4.5		µs
t_s	Output voltage settling time⁽²⁾	100h to 300h code change R_L = 2 kΩ, C_L = 200 pF	T_MIN ≤ T_A ≤ T_MAX			6	µs
SR	Output slew rate				1		V/µs
	Glitch impulse	Code change from 200h to 1FFh			12		nV-sec
	Digital feedthrough				0.5		nV-sec
	Digital crosstalk				1		nV-sec
	DAC-to-DAC crosstalk				3		nV-sec
	Multiplying bandwidth	V_REFIN = 2.5 V ± 0.1 Vpp			160		kHz
	Total harmonic distortion	V_REFIN = 2.5 V ± 0.1 Vpp input frequency = 10 kHz			70		dB
t_WU	Wake-up time	V_A = 3 V			6		µsec
t_WU	Wake-up time	V_A = 5 V			39		µsec
1/f_SCLK	SCLK cycle time				25		ns
1/f_SCLK	SCLK cycle time	T_MIN ≤ T_A ≤ T_MAX		33			ns
t_CH	SCLK high time				7		ns
t_CH	SCLK high time	T_MIN ≤ T_A ≤ T_MAX		10			ns
t_CL	SCLK low Time				7		ns
t_CL	SCLK low Time	T_MIN ≤ T_A ≤ T_MAX		10			ns
t_SS	SYNC set-up time prior to SCLK falling edge				4		ns
t_SS	SYNC set-up time prior to SCLK falling edge	T_MIN ≤ T_A ≤ T_MAX		10			ns
t_DS	Data set-up time prior to SCLK falling edge				1.5		ns
t_DS	Data set-up time prior to SCLK falling edge	T_MIN ≤ T_A ≤ T_MAX		3.5			ns
t_DH	Data hold time after SCLK falling edge				1.5		ns
t_DH	Data hold time after SCLK falling edge	T_MIN ≤ T_A ≤ T_MAX		3.5			ns
t_CFSR	SCLK fall prior to rise of SYNC				0		ns
t_CFSR	SCLK fall prior to rise of SYNC	T_MIN ≤ T_A ≤ T_MAX		3			ns
t_SYNC	SYNC high time				6		ns
t_SYNC	SYNC high time	T_MIN ≤ T_A ≤ T_MAX		10			ns

(1) Typical figures are at T_J = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing Quality Level).

(2) This parameter is ensured by design and/or characterization and is not tested in production.