SNAS364F May   2006  – April 2016 DAC102S085

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 AC and Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DAC Section
      2. 8.3.2 Output Amplifiers
      3. 8.3.3 Reference Voltage
      4. 8.3.4 Power-On Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Modes
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
      2. 8.5.2 Input Shift Register
      3. 8.5.3 DSP and Microprocessor Interfacing
        1. 8.5.3.1 ADSP-2101 and ADSP-2103 Interfacing
        2. 8.5.3.2 80C51 and 80L51 Interface
        3. 8.5.3.3 68HC11 Interface
        4. 8.5.3.4 Microwire Interface
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Bipolar Operation
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Using References as Power Supplies
      1. 10.1.1 LM4130
      2. 10.1.2 LM4050
      3. 10.1.3 LP3985
      4. 10.1.4 LP2980
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
        1. 12.1.1.1 Specification Definitions
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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7 Specifications

7.1 Absolute Maximum Ratings

See (1)(2)(3)
MIN MAX UNIT
Supply voltage VA 6.5 V
Voltage DIN, SCLK, SYNC, VREFIN −0.3 6.5 V
Input current(4) 10 mA
Package input current(4) 20 mA
Power consumption at TA = 25°C See(5)
Junction temperature, TJ 150 °C
Storage temperature, Tstg −65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications.
(3) All voltages are measured with respect to GND = 0 V, unless otherwise specified.
(4) When the input voltage at any pin exceeds 5.5 V or is less than GND, the current at that pin should be limited to 10 mA. The 20-mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of
10 mA to two.
(5) The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (RθJA), and the ambient temperature (TA), and can be calculated using the formula PDmax = (TJmax - TA) / RθJA.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

See (1)
MIN MAX UNIT
Operating temperature –40 105 °C
VA Supply voltage 2.7 5.5 V
VREFIN Reference voltage 1 VA V
Digital input voltage(2) 0 5.5 V
Output load 0 1500 pF
SCLK frequency 40 MHz
(1) All voltages are measured with respect to GND = 0 V, unless otherwise specified.
(2) The inputs are protected. Input voltage magnitudes up to 5.5 V, regardless of VA, do not cause errors in the conversion result. For example, if VA is 3 V, the digital input pins can be driven with a 5-V logic device.

7.4 Thermal Information

THERMAL METRIC(1) DAC102S085 UNIT
DGS (VSSOP) DSC (WSON)
10 PINS 10 PINS
RθJA Junction-to-ambient thermal resistance 240 250 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

The following specifications apply for VA = 2.7 V to 5.5 V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 12 to 1011. Minimum and Maximum limits apply for TA = –40°C to 105°C, Typical values apply for TA = 25°C, unless otherwise specified. Test limist are specified to AOQL (Average Outgoing Quality Level).(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE
Resolution 10 Bits
Monotonicity 10 Bits
INL Integral non-linearity ±0.7 ±2 LSB
DNL Differential non-linearity VA = 2.7 V to 5.5 V TA = 25°C –0.03 0.08 LSB
TA = –40°C to 105°C –0.25 0.35
ZE Zero code error IOUT = 0 5 15 mV
FSE Full-scale error IOUT = 0 −0.1 −0.75 %FSR
GE Gain error All ones loaded to DAC register −0.2 −1 %FSR
ZCED Zero code error drift −20 µV/°C
TC GE Gain error tempco VA = 3 V −0.7 ppm/°C
VA = 5 V −1
OUTPUT CHARACTERISTICS
Output voltage range 0 VREFIN V
IOZ High-impedance output leakage current ±1 µA
ZCO Zero code output VA = 3 V, IOUT = 200 µA 1.3 mV
VA = 3 V, IOUT = 1 mA 6
VA = 5 V, IOUT = 200 µA 7
VA = 5 V, IOUT = 1 mA 10
FSO Full scale output VA = 3 V, IOUT = 200 µA 2.984 V
VA = 3 V, IOUT = 1 mA 2.934
VA = 5 V, IOUT = 200 µA 4.989
VA = 5 V, IOUT = 1 mA 4.958
IOS Output short-circuit current (source) VA = 3 V, VOUT = 0 V, Input Code = 3FFh –56 mA
VA = 5 V, VOUT = 0 V, Input Code = 3FFh –69
IOS Output short-circuit current (sink) VA = 3 V, VOUT = 3 V, Input Code = 000h 52 mA
VA = 5 V, VOUT = 5 V, Input Code = 000h 75
IO Continuous output current Available on each DAC output 11 mA
CL Maximum load capacitance RL = ∞ 1500 pF
RL = 2 kΩ 1500
ZOUT DC output impedance 7.5 Ω
REFERENCE INPUT CHARACTERISTICS
VREFIN Input range minimum 0.2 1 V
Input range maximum VA
ZIN Input impedance 60 kΩ
LOGIC INPUT CHARACTERISTICS
IIN Input current ±1 µA
VIL Input low voltage VA = 3 V 0.9 0.6 V
VA = 5 V 1.5 0.8
VIH Input high voltage VA = 3 V 1.4 2.1 V
VA = 5 V 2.1 2.4
CIN Input capacitance 3 pF
POWER REQUIREMENTS
IN Normal supply current (output unloaded) fSCLK = 30 MHz VA = 2.7 V to 3.6 V 210 270 µA
VA = 4.5 V to 5.5 V 320 410
fSCLK = 0 MHz VA = 2.7 V to 3.6 V 190
VA = 4.5 V to 5.5 V 290
IPD Power-down supply current (output unloaded, SYNC = DIN = 0 V after PD mode loaded) All PD Modes VA = 2.7 V to 3.6 V 0.1 1 µA
VA = 4.5 V to 5.5 V 0.15 1
PN Normal supply power (output unloaded) fSCLK = 30 MHz VA = 2.7 V to 3.6 V 0.6 1 mW
VA = 4.5 V to 5.5 V 1.6 2.3
fSCLK = 0 MHz VA = 2.7 V to 3.6 V 0.6
VA = 4.5 V to 5.5 V 1.5
PPD Power down supply current (output unloaded, SYNC = DIN = 0 V after PD mode loaded) All PD Modes VA = 2.7 V to 3.6 V 0.3 3.6 µW
VA = 4.5 V to 5.5 V 0.8 5.5
(1) To ensure accuracy, it is required that VA and VREFIN be well bypassed.

7.6 AC and Timing Requirements

Values shown in this table are design targets and are subject to change before product release.
The following specifications apply for VA = 2.7 V to 5.5 V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 12 to 1011. Minimum and Maximum limits apply for TA = –40°C to 105°C, Typical values apply for TA = 25°C, unless otherwise specified. Test limist are specified to AOQL (Average Outgoing Quality Level).
MIN TYP MAX UNIT
fSCLK SCLK frequency 40 30 MHz
ts Output voltage settling time 100h to 300h code change
RL = 2 kΩ, CL = 200 pF		 4.5 6 µs
SR Output slew rate 1 V/µs
Glitch impulse Code change from 200h to 1FFh 12 nV-sec
Digital feedthrough 0.5 nV-sec
Digital crosstalk 1 nV-sec
DAC-to-DAC crosstalk 3 nV-sec
Multiplying bandwidth VREFIN = 2.5 V ± 0.1 VPP 160 kHz
Total harmonic distortion VREFIN = 2.5 V ± 1.0 VPP
input frequency = 10 kHz		 70 dB
tWU Wake-up time VA = 3 V 6 µs
VA = 5 V 39
1/fSCLK SCLK cycle time 33 25 ns
tCH SCLK high time 10 7 ns
tCL SCLK low time 10 7 ns
tSS SYNC setup time prior to SCLK falling edge 10 4 ns
tDS Data setup time prior to SCLK falling edge 3.5 1.5 ns
tDH Data hold time after SCLK falling edge 3.5 1.5 ns
tCFSR SCLK fall prior to rise of SYNC 3 0 ns
tSYNC SYNC high time 10 6 ns
DAC102S085 20195505.gif Figure 1. I/O Transfer Characteristic
DAC102S085 20195506.gif Figure 2. Serial Timing Diagram

7.7 Typical Characteristics

VREF = VA, fSCLK = 30 MHz, TA = 25C, Input Code Range 12 to 1011, unless otherwise stated
DAC102S085 20195552.png Figure 3. INL at VA = 3 V
DAC102S085 20195554.png Figure 5. DNL at VA = 3 V
DAC102S085 20195556.png Figure 7. INL and DNL vs VREFIN at VA = 3 V
DAC102S085 20195550.png Figure 9. INL and DNL vs fSCLK at VA = 2.7 V
DAC102S085 20195524.png Figure 11. INL and DNL vs Clock Duty Cycle at VA = 3 V
DAC102S085 20195526.png Figure 13. INL and DNL vs Temperature at VA = 3 V
DAC102S085 20195530.png Figure 15. Zero Code Error vs VA
DAC102S085 20195534.png Figure 17. Zero Code Error vs fSCLK
DAC102S085 20195536.png Figure 19. Zero Code Error vs Temperature
DAC102S085 20195532.png Figure 21. Full-Scale Error vs VREFIN
DAC102S085 20195538.png Figure 23. Full-Scale Error vs Clock Duty Cycle
DAC102S085 20195544.png Figure 25. Supply Current vs VA
DAC102S085 20195546.png Figure 27. 5-V Glitch Response
DAC102S085 20195548.png Figure 29. 3-V Wakeup Time
DAC102S085 20195553.png Figure 4. INL at VA = 5 V
DAC102S085 20195555.png Figure 6. DNL at VA = 5 V
DAC102S085 20195557.png Figure 8. INL and DNL vs VREFIN at VA = 5 V
DAC102S085 20195522.png Figure 10. INL and DNL vs VA
DAC102S085 20195525.png Figure 12. INL and DNL vs Clock Duty Cycle at VA = 5 V
DAC102S085 20195527.png Figure 14. INL and DNL vs Temperature at VA = 5 V
DAC102S085 20195531.png Figure 16. Zero Code Error vs VREFIN
DAC102S085 20195535.png Figure 18. Zero Code Error vs Clock Duty Cycle
DAC102S085 20195537.png Figure 20. Full-Scale Error vs VA
DAC102S085 20195533.png Figure 22. Full-Scale Error vs fSCLK
DAC102S085 20195539.png Figure 24. Full-Scale Error vs Temperature
DAC102S085 20195545.png Figure 26. Supply Current vs Temperature
DAC102S085 20195547.png Figure 28. Power-On Reset
DAC102S085 20195549.png Figure 30. 5-V Wakeup Time