SNAS449F February   2008  – May 2017 DAC081C081 , DAC081C085

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1. 3.1 Block Diagram
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 AC and Timing Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DAC Section
      2. 8.3.2 Output Amplifier
      3. 8.3.3 Reference Voltage
      4. 8.3.4 Power-On Reset
      5. 8.3.5 Simultaneous Reset
      6. 8.3.6 Additional Timing Information: toutz
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Modes
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
      2. 8.5.2 Basic I2C Protocol
      3. 8.5.3 Standard-Fast Mode
      4. 8.5.4 High-Speed (Hs) Mode
      5. 8.5.5 I2C Slave (Hardware) Address
      6. 8.5.6 Writing to the DAC Register
      7. 8.5.7 Reading from the DAC Register
    6. 8.6 Registers
      1. 8.6.1 DAC Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Bipolar Operation
      2. 9.1.2 DSP/Microprocessor Interfacing
        1. 9.1.2.1 Interfacing to the 2-Wire Bus
        2. 9.1.2.2 Interfacing to a Hs-mode Bus
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Using References as Power Supplies
      1. 10.1.1 LM4132
      2. 10.1.2 LM4050
      3. 10.1.3 LP3985
      4. 10.1.4 LP2980
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
      2. 12.1.2 Device Nomenclature
        1. 12.1.2.1 Specification Definitions
    2. 12.2 Related Links
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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7 Specifications

7.1 Absolute Maximum Ratings

See (1)(2)(5)
MIN MAX UNIT
Supply voltage, VA −0.3 6.5 V
Voltage on any Input Pin −0.3 6.5 V
Input current at any pin(3) ±10 mA
Package input current(3) ±20 mA
Power consumption at TA = 25°C See (4)
Junction temperature 150 °C
Storage temperature, Tstg −65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are measured with respect to GND = 0 V, unless otherwise specified.
(3) When the input voltage at any pin exceeds 5.5 V or is less than GND, the current at that pin should be limited to 10 mA. The 20-mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two.
(4) The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (RθJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA) / RθJA. The values for maximum power dissipation will be reached only when the device is operated in a severe fault condition (for example, when input or output pins are driven beyond the operating ratings, or the power supply polarity is reversed).
(5) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.

7.2 ESD Ratings

VALUE UNIT
DAC081C081 in NGF Package
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 All pins except 2 and 3 ±2500 V
Pins 2 and 3 ±5000
Charged-device model (CDM), per JEDEC specification JESD22-C101 All pins except 2 and 3 ±1000
Pins 2 and 3 ±1000
Machine model (MM) All pins except 2 and 3 ±250
Pins 2 and 3 ±350
DAC081C081 in DDC Package
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 All pins except 4 and 5 ±2500 V
Pins 4 and 5 ±5000
Charged-device model (CDM), per JEDEC specification JESD22-C101 All pins except 4 and 5 ±1000
Pins 4 and 5 ±1000
Machine model (MM) All pins except 4 and 5 ±250
Pins 4 and 5 ±350
DAC081C085 in DGK Package
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 All pins except 3 and 4 ±2500 V
Pins 3 and 4 ±5000
Charged-device model (CDM), per JEDEC specification JESD22-C101 All pins except 3 and 4 ±1000
Pins 3 and 4 ±1000
Machine model (MM) All pins except 3 and 4 ±250
Pins 3 and 4 ±350

7.3 Recommended Operating Conditions

See (1)
MIN NOM MAX UNIT
Operating Temperature −40 TA 125 °C
Supply Voltage, VA 2.7 5.5 V
Reference Voltage, VREFIN 1 VA V
Digital Input Voltage(2) 5.5 V
Output Load 0 1500 pF
(1) All voltages are measured with respect to GND = 0 V, unless otherwise specified.
(2) The inputs are protected as shown below. Input voltage magnitudes up to 5.5 V, regardless of VA, will not cause errors in the conversion result. For example, if VA is 3 V, the digital input pins can be driven with a 5V logic device.
DAC081C081 DAC081C085 30052304.gif

7.4 Thermal Information

THERMAL METRIC(1)(2) DAC081C081 DAC081C085 UNIT
NGF (WSON) DDC (SOT) DGK (VSSOP)
6 PINS 6 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 190 250 240 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
(2) Soldering process must comply with Reflow Temperature Profile specifications. Refer to http://www.ti.com/packaging.
Reflow temperature profiles are different for lead-free packages.

7.5 Electrical Characteristics

The following specifications apply for VA = 2.7 V to 5.5 V, VREF = VA, CL = 200 pF to GND, input code range 3 to 252. All Maximum and Minimum limits apply for TMIN ≤ TA ≤ TMAX and all Typical limits are at TA = 25°C, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP(1) MAX(1) UNIT
STATIC PERFORMANCE
INL Resolution 8 Bits
Monotonicity 8 Bits
Integral non-linearity 0.14 0.6 LSB
−0.6 −0.14 LSB
DNL Differential non-linearity 0.04 0.1 LSB
−0.1 −0.02 LSB
ZE Zero code error IOUT = 0 1.1 10 mV
FSE Full-scale error IOUT = 0 −0.1 −0.7 %FSR
GE Gain error All ones loaded to DAC register −0.2 −0.7 %FSR
ZCED Zero code error drift −20 µV/°C
TC GE Gain error tempco VA = 3 V −0.7 ppm FSR/°C
VA = 5 V −1 ppm FSR/°C
ANALOG OUTPUT CHARACTERISTICS (VOUT)
Output voltage range(2) DAC081C085 0 VREF V
DAC081C081 0 VA V
ZCO Zero code output VA = 3 V, IOUT = 200 µA 1.3 mV
VA = 5 V, IOUT = 200 µA 7 mV
FSO Full-scale output VA = 3 V, IOUT = 200 µA 2.984 V
VA = 5 V, IOUT = 200 µA 4.989 V
IOS Output short circuit current
(ISOURCE)		 VA = 3 V, VOUT = 0 V, input code = FFFh. 56 mA
VA = 5 V, VOUT = 0 V, input code = FFFh. 69 mA
IOS Output short circuit current
(ISINK)		 VA = 3 V, VOUT = 3 V, input code = 000h. −52 mA
VA = 5 V, VOUT = 5 V, input code = 000h. −75 mA
IO Continuous output
current(2)		 Available on the DAC output 11 mA
CL Maximum load capacitance RL = ∞ 1500 pF
RL = 2kΩ 1500 pF
ZOUT DC output impedance 7.5 Ω
REFERENCE INPUT CHARACTERISTICS- (DAC081C085 only)
VREF Input range minimum 1 0.2 V
Input range maximum VA V
Input impedance 120 kΩ
LOGIC INPUT CHARACTERISTICS (SCL, SDA)
VIH Input high voltage 0.7 × VA V
VIL Input low voltage 0.3 × VA V
IIN Input current ±1 µA
CIN Input pin capacitance(2) 3 pF
VHYST Input hysteresis 0.1 × VA V
LOGIC INPUT CHARACTERISTICS (ADR0, ADR1)
VIH Input high voltage VA – 0.5 V
VIL Input low voltage 0.5 V
IIN Input current ±1 µA
LOGIC OUTPUT CHARACTERISTICS (SDA)
VOL Output low voltage ISINK = 3 mA 0.4 V
ISINK = 6 mA 0.6 V
IOZ High-impedence output
leakage current 		±1 µA
POWER REQUIREMENTS
VA Supply voltage minimum 2.7 V
Supply voltage maximum 5.5
NORMAL -- VOUT SET TO MIDSCALE. 2-WIRE INTERFACE QUIET (SCL = SDA = VA) (OUTPUT UNLOADED)
IST_VA-1 VA DAC081C081 supply current VA = 2.7 V to 3.6 V 105 156 µA
VA = 4.5 V to 5.5 V 132 214 µA
IST_VA-5 VA DAC081C085 supply current VA = 2.7 V to 3.6 V 86 118 µA
VA = 4.5 V to 5.5 V 98 152 µA
IST_VREF VREF supply current
(DAC081C085 only)		 VA = 2.7 V to 3.6 V 37 43 µA
VA = 4.5 V to 5.5 V 53 61 µA
PST Power consumption
(VA & VREF for DAC081C085) 		VA = 3 V 380 µW
VA = 5 V 730 µW
CONTINUOUS OPERATION -- 2-WIRE INTERFACE ACTIVELY ADDRESSING THE DAC AND WRITING TO THE DAC REGISTER (OUTPUT UNLOADED)
ICO_VA-1 VA DAC081C081 supply current fSCL = 400 kHz VA = 2.7 V to 3.6 V 134 220 µA
VA = 4.5 V to 5.5 V 192 300 µA
fSCL = 3.4 MHz VA = 2.7 V to 3.6 V 225 320 µA
VA = 4.5 V to 5.5 V 374 500 µA
ICO_VA-5 VA DAC081C085 supply current fSCL = 400 kHz VA = 2.7 V to 3.6 V 101 155 µA
VA = 4.5 V to 5.5 V 142 220 µA
fSCL = 3.4 MHz VA = 2.7 V to 3.6 V 193 235 µA
VA = 4.5 V to 5.5 V 325 410 µA
ICO_VREF VREF supply current
(DAC081C085 only)		 VA = 2.7 V to 3.6 V 33.5 55 µA
VA = 4.5 V to 5.5 V 49.5 71.4 µA
PCO Power consumption
(VA and VREF for DAC081C085) 		fSCL = 400 kHz VA = 3 V 480 µW
VA = 5 V 1.06 mW
fSCL = 3.4 MHz VA = 3 V 810 µW
VA = 5 V 2.06 mW
POWER DOWN -- 2-WIRE INTERFACE QUIET (SCL = SDA = VA) AFTER PD MODE WRITTEN TO DAC REGISTER (OUTPUT UNLOADED)
IPD Supply current
(VA and VREF for DAC081C085)		 All power-down modes VA = 2.7 V to 3.6 V 0.13 1.52 µA
VA = 4.5 V to 5.5 V 0.15 3.25 µA
PPD Power consumption
(VA and VREF for DAC081C085)		 All power-down modes VA = 3 V 0.5 µW
VA = 5 V 0.9 µW
(1) Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing Quality Level).
(2) This parameter is ensured by design and/or characterization and is not tested in production.

7.6 AC and Timing Characteristics

The following specifications apply for VA = 2.7 V to 5.5 V, VREF = VA, RL = Infinity, CL = 200 pF to GND. All Maximum and Minimum limits apply for TMIN ≤ TA ≤ TMAX and all Typical limits are at TA = 25°C, unless otherwise specified.
PARAMETER TEST CONDITIONS(5) MIN TYP(1) MAX(5)(1) UNIT
ts Output voltage settling time(2) 40h to C0h code change
RL = 2 kΩ, CL = 200 pF		 3 4.5 µs
SR Output slew rate 1 V/µs
Glitch impulse Code change from 80h to 7Fh 12 nV-sec
Digital feedthrough 0.5 nV-sec
Multiplying bandwidth(4) VREF = 2.5 V ± 0.1 Vpp 160 kHz
Total harmonic distortion(4) VREF = 2.5 V ± 0.1 Vpp
input frequency = 10 kHz		 70 dB
tWU Wake-up time VA = 3 V 0.8 µsec
VA = 5 V 0.5 µsec
DIGITAL TIMING SPECS (SCL, SDA)
fSCL Serial clock frequency Standard mode 100 kHz
Fast mode 400
High-speed mode, Cb = 100 pF 3.4 MHz
High-speed mode, Cb = 400 pF 1.7
tLOW SCL low time Standard mode 4.7 µs
Fast mode 1.3
High-speed mode, Cb = 100 pF 160 ns
High-speed mode, Cb = 400 pF 320
tHIGH SCL high time Standard mode 4 µs
Fast mode 0.6
High-speed mode, Cb = 100 pF 60 ns
High-speed mode, Cb = 400 pF 120
tSU;DAT Data set-up time Standard mode 250 ns
Fast mode 100
High-speed mode 10
tHD;DAT Data hold time Standard mode 0 3.45 µs
Fast mode 0 0.9
High-speed mode, Cb = 100 pF 0 70 ns
High-speed mode, Cb = 400 pF 0 150
tSU;STA Set-up time for a start or a repeated start condition Standard mode 4.7 µs
Fast mode 0.6
High-speed mode 160 ns
tHD;STA Hold time for a start or a repeated start condition Standard mode 4 µs
Fast mode 0.6
High-speed mode 160 ns
tBUF Bus free time between a stop and start condition Standard mode 4.7 µs
Fast mode 1.3
tSU;STO Set-up time for a stop condition Standard mode 4 µs
Fast mode 0.6
High-speed mode 160 ns
trDA Rise time of SDA signal Standard mode 1000 ns
Fast mode 20 + 0.1 Cb 300
High-speed mode, Cb = 100 pF 10 80
High-speed mode, Cb = 400 pF 20 160
tfDA Fall time of SDA signal Standard mode 250 ns
Fast mode 20 + 0.1 Cb 250
High-speed mode, Cb = 100 pF 10 80
High-speed mode, Cb = 400 pF 20 160
trCL Rise time of SCL signal Standard mode 1000 ns
Fast mode 20 + 0.1 Cb 300
High-speed mode, Cb = 100 pF 10 40
High-speed mode, Cb = 400 pF 20 80
trCL1 Rise time of SCL signal after a repeated start condition and after an acknowledge bit. Standard mode 1000 ns
Fast mode 20 + 0.1 Cb 300
High-speed mode, Cb = 100 pF 10 80
High-speed mode, Cb = 400 pF 20 160
tfCL Fall time of a SCL signal Standard mode 300 ns
Fast mode 20 + 0.1 Cb 300
High-speed mode, Cb = 100 pF 10 40
High-speed mode, Cb = 400 pF 20 80
Cb Capacitive load for each bus line (SCL and SDA) 400 pF
tSP Pulse width of spike suppressed(3)(2) Fast mode 50 ns
High-speed mode 10
toutz SDA output delay (see Additional Timing Information: toutz) Fast mode 87 270 ns
High-speed mode 38 60
(1) Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing Quality Level).
(2) This parameter is ensured by design and/or characterization and is not tested in production.
(3) Spike suppression filtering on SCL and SDA will supress spikes that are less than 50ns for standard-fast mode and less than 10ns for hs-mode.
(4) Applies to the Multiplying DAC configuration. In this configuration, the reference is used as the analog input. The value loaded in the DAC Register will digitally attenuate the signal at Vout.
(5) Cb refers to the capacitance of one bus line. Cb is expressed in pF units.
DAC081C081 DAC081C085 30052305.gif Figure 1. Input / Output Transfer Characteristic
DAC081C081 DAC081C085 30052360.gif Figure 2. Serial Timing Diagram

7.7 Typical Characteristics

VREF = VA, fSCL = 3.4 MHz, TA = 25°C, Input Code Range 3 to 252, unless otherwise stated.
DAC081C081 DAC081C085 30052320.png Figure 3. INL
DAC081C081 DAC081C085 30052322.png Figure 5. INL/DNL vs Temperature at VA = 3 V
DAC081C081 DAC081C085 30052324.png Figure 7. INL/DNL vs VREFIN at VA = 3 V
DAC081C081 DAC081C085 30052326.png Figure 9. INL/DNL vs VA
DAC081C081 DAC081C085 30052328.png Figure 11. Zero Code Error vs Temperature
DAC081C081 DAC081C085 30052329.png Figure 13. Full Scale Error vs Temperature
DAC081C081 DAC081C085 30052331.png Figure 15. VREF Supply Current vs VA
DAC081C081 DAC081C085 30052333.png Figure 17. Total Supply Current vs Temperature at VA = 5 V
DAC081C081 DAC081C085 30052335.png Figure 19. Power-ON Reset
DAC081C081 DAC081C085 30052321.png Figure 4. DNL
DAC081C081 DAC081C085 30052323.png Figure 6. INL/DNL vs Temperature at VA = 5 V
DAC081C081 DAC081C085 30052325.png Figure 8. INL/DNL vs VREFIN at VA = 5 V
DAC081C081 DAC081C085 30052327.png Figure 10. Zero Code Error vs VA
DAC081C081 DAC081C085 30052336.png Figure 12. Full Scale Error vs VA
DAC081C081 DAC081C085 30052330.png Figure 14. Total Supply Current vs VA
DAC081C081 DAC081C085 30052332.png Figure 16. Total Supply Current vs Temperature at VA = 3 V
DAC081C081 DAC081C085 30052334.png Figure 18. 5-V Glitch Response